CHAPTER 3 CPU

3.4.3Multiple Interrupts

Multiple interrupts are allowed by setting different levels into the interrupt level setting registers (ILR1 to ILR4) for multiple interrupt requests from peripheral functions.

■Multiple Interrupts

When an interrupt request with a higher interrupt level is generated while the interrupt processing routine is operating, the current interrupt processing cycle is stopped to accept the higher-level interrupt request. Interrupt levels 1, 2, and 3 can be specified. Level 3 prohibits the CPU from accepting interrupts.

●Example of multiple interrupts

As an example of multiple-interrupt processing, suppose a case in which a timer interrupt has precedence using the A/D interrupt, and the A/D interrupt level is set to level 2 and the timer interrupt level is set to level 1. Figure 3.4-3shows the sequence performed when an external interrupt is generated while an A/D interrupt is being processed.

Figure 3.4-3 Example of Multiple Interrupts

Main program

A/D interrupt

Timer interrupt

 

 

 

processing

processing

 

 

 

 

 

Interrupt

 

 

 

 

 

 

 

 

 

Initializes

 

Interrupt

 

 

level 1

 

 

 

 

 

 

 

 

 

 

 

peripherals

 

 

 

Timer interrupt

 

Timer interrupt

 

 

level 2

 

 

generated

 

A/D interrupt

 

 

Stop

 

 

processed

 

 

 

 

 

generated

 

 

process-

 

 

 

 

 

 

 

 

 

 

 

 

ing

 

 

 

 

 

 

 

 

 

Resumes

 

 

 

 

 

 

 

 

processing

 

A/D interrupt

 

Return from

 

 

 

 

 

 

 

 

 

timer interrupt

 

 

 

 

 

 

Main

 

 

 

 

processed

 

processing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

program

 

 

 

 

Return from A/D

 

 

 

 

 

 

 

 

restarts

 

 

 

 

 

 

 

 

 

 

interrupt processing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

•In the A/D interrupt processing, the interrupt level bits in the condition code register (CCR: IL1 and IL0) are set to the same value as the value in the interrupt level setting register corresponding to the A/ D interrupt (ILR1, 2, 3, or 4) (i.e., 2 in this example). If an interrupt request with a higher interrupt level specified is generated (1 in this example), processing for the higher interrupt level is effected first.

•To temporarily prohibit multiple interrupts in the A/D interrupt processing, turn off the interrupt enable flag (CCR: I = 0) in the condition code register, or set 00B to the interrupt level bits (IL1 and IL0).

•Executing the return instruction (RETI) after interrupt processing restores the values of the program counter (PC) and program status (PS) and ensures resumption of the interrupted program.

•The value in the condition code register (CCR) is returned to the value used before interruption when the program status (PS) value is restored.

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Fujitsu F202RA, MB89202 manual Multiple Interrupts, Example of multiple interrupts
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F202RA, MB89202 specifications

The Fujitsu MB89202 and F202RA microcontrollers are part of the 16-bit microcontroller family, renowned for their robust performance and versatility in a variety of embedded system applications. These devices are tailored for high-efficiency operation across diverse industries, including automotive, consumer electronics, and industrial automation.

One of the main features of the MB89202 is its powerful CPU core, which operates at a clock speed of up to 20 MHz. This enables the microcontroller to perform complex calculations and consumer-grade applications seamlessly. The architecture is designed to handle multiple tasks effectively, making it suitable for real-time operations.

Memory capacity is a vital characteristic of the MB89202, featuring on-chip RAM and ROM configurations. The microcontroller can accommodate different memory variants, providing developers with flexibility in memory allocation based on their application requirements. This adaptability facilitates applications ranging from simple control systems to complex data processing tasks.

The F202RA variant extends the capabilities of the MB89202 by integrating advanced peripheral functions. It includes built-in timers, A/D converters, and serial communication interfaces, which are essential for interfacing with other hardware components or sensors. The availability of these peripherals reduces the need for additional external circuits, thus contributing to a more compact and cost-effective design.

In terms of power management, the MB89202 series employs advanced power-saving technologies. The microcontroller offers various low-power modes, enabling devices to conserve energy during idle times, making it highly suitable for battery-operated applications. This characteristic not only enhances the efficiency of devices but also extends their operational lifespan.

Moreover, the Fujitsu MB89202 series incorporates robust protection features, including watchdog timers and failure detection mechanisms. These safety features ensure reliable operation in critical systems, making them a preferred choice in applications where failure is not an option.

The MB89202 and F202RA microcontrollers also support a range of development tools and environments, including integrated development environments (IDEs) and software libraries, which facilitate rapid application development. With these tools, developers can efficiently prototype, debug, and optimize their applications.

In summary, the Fujitsu MB89202 and F202RA microcontrollers stand out with their efficient performance, extensive memory options, integrated peripherals, and power-saving capabilities, making them ideal for a wide array of embedded applications. Their reliability and robustness further enhance their attractiveness for designers seeking advanced microcontroller solutions.
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