CHAPTER 3 CPU

The interrupt controller is always monitoring interrupt requests from peripheral functions. The interrupt controller notifies the CPU of the highest interrupt level interrupt among levels corresponding to interrupt requests currently generated. If different requests are made with the same interrupt level, the interrupt controller also determines their priorities.

The CPU checks the value in the interrupt enable flag (CCR: I) when the priority of the interrupt level that is received is higher (the level value is lower) than the level specified in the interrupt level bits in the condition code register (CCR: IL1 and IL0). The CPU then accepts the interrupt when the enable flag is turned on (CCR: I = 1).

Put the values in the program counter (PC) and program status (PS) in the stack, fetch the start address of the interrupt processing routine from the interrupt vector table concerned, change the value of the interrupt level bits in the condition code register (CCR: IL1 and IL0) to the value of the interrupt level accepted, and then start the interrupt processing routine.

Finally, restore the values of the program counter (PC) and program status (PS) put into the stack with the RETI instruction, then execute an instruction following the instruction executed immediately before the interruption.

Standby mode (low-power consumption mode) is cancelled by an interrupt. For details, see Section "3.7

Standby Mode (Low-Power Consumption Mode) ".

Notes:

An interrupt request flag bit for a peripheral function is not automatically cleared even if the interrupt request is accepted. Therefore, it is necessary to clear the bit using a program in the interrupt processing routine (by writing "0" into the interrupt request flag bit normally).

Clearing an interrupt request flag bit at the beginning of the interrupt processing routine allows the peripheral function that generated the interrupt to re-generate an interrupt (set an interrupt request flag bit again) while the interrupt processing routine is being executed. However, the re-generated interrupt is normally accepted after the interrupt processing routine ends its current cycle.

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Fujitsu MB89202, F202RA manual Cpu

F202RA, MB89202 specifications

The Fujitsu MB89202 and F202RA microcontrollers are part of the 16-bit microcontroller family, renowned for their robust performance and versatility in a variety of embedded system applications. These devices are tailored for high-efficiency operation across diverse industries, including automotive, consumer electronics, and industrial automation.

One of the main features of the MB89202 is its powerful CPU core, which operates at a clock speed of up to 20 MHz. This enables the microcontroller to perform complex calculations and consumer-grade applications seamlessly. The architecture is designed to handle multiple tasks effectively, making it suitable for real-time operations.

Memory capacity is a vital characteristic of the MB89202, featuring on-chip RAM and ROM configurations. The microcontroller can accommodate different memory variants, providing developers with flexibility in memory allocation based on their application requirements. This adaptability facilitates applications ranging from simple control systems to complex data processing tasks.

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