Intel PXA26X manuals
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When we buy new device such as Intel PXA26X we often through away most of the documentation but the warranty.
Very often issues with Intel PXA26X begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Laptop Intel PXA26X is responsible for and what options to choose for expected result.
Fortunately you can find all manuals for Laptop on our side using links below.
624 pages 4.33 Mb
ii Intel PXA26x Processor Family D evel ope rs M an ual 2 Contents3 Contents25 Introduction 131 System Architecture 267 Clocks and Power Manager 3109 System Integration Unit 4159 Direct Memory Access Controller 5191 Memory Controller 6269 Liquid Crystal Display Controller 7319 Synchronous Serial Port Controller 8339 Inter-Integrated Circuit Bus Interface Unit 9367 Universal Asynchronous Receiver/ Transmitter 10395 Fast Infrared Communication Port 11411 Universal Serial Bus Device Controller 1212.1 Universal Serial Bus Overview 412 12.2 Device Configuration413 12.3 Universal Serial Bus Protocol420 12.4 UDC Hardware Connection12.4.1 Self-Powered Device 12.4.2 Bus-Powered Devices 422 12.5 UDC Operation431 12.6 UDC Register Descriptions432 12.6.1 UDC Control Register12.6.1.1 UDC Enable 12.6.1.2 UDC Active 12.6.1.3 UDC Resume (RSM) 12.6.1.4 Resume Interrupt Request (RESIR) 12.6.1.5 Suspend Interrupt Request (SUSIR) 12.6.1.6 Suspend/Resume Interrupt Mask (SRM) 433 12.6.1.7 Reset Interrupt Request (RSTIR)12.6.1.8 Reset Interrupt Mask (REM) 434 12.6.2 UDC Endpoint 0 Control/Status Register (UDCCS0)12.6.2.1 OUT Packet Ready (OPR) 12.6.2.2 IN Packet Ready (IPR)12-26 Intel PXA26x Processor Family Developers Manual 436 12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 1112.6.3.1 Transmit FIFO Service (TFS)Table 12-13. UDC Endpoint 0 Control Status Register 437 12.6.3.2 Transmit Packet Complete (TPC)12.6.3.3 Flush Tx FIFO (FTF) 12.6.3.4 Transmit Underrun (TUR) 12.6.3.5 Sent STALL (SST) 12.6.3.6 Force STALL (FST) 12.6.3.7 Bit 6 Reserved12-28 Intel PXA26x Processor Family Developers Manual 12.6.3.8 Transmit Short Packet (TSP) 438 12.6.4 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 2, 7, or 12441 12.6.5 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 3, 8, or 1312.6.5.1 Transmit FIFO Service (TFS) 12.6.5.2 Transmit Packet Complete (TPC)Intel PXA26x Processor Family Developers Manual 12-33 443 12.6.6 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 4, 9, or 1412.6.6.1 Receive FIFO Service (RFS)Table 12-16. UDC Endpoint x Control Status Register, Where x is 3, 8, or 13Intel PXA26x Processor Family Developers Manual 12-35 445 12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 5, 10, or 15.12.6.7.1 Transmit FIFO Service (TFS)Table 12-17. UDC Endpoint x Control Status Register, Where x is 4, 9, or 14 446 12.6.7.2 Transmit Packet Complete (TPC)12.6.7.3 Flush Tx FIFO (FTF) 12.6.7.4 Transmit Underrun (TUR) 12.6.7.5 Sent STALL (SST) 12.6.7.6 Force STALL (FST) 12.6.7.7 Bit 6 ReservedIntel PXA26x Processor Family Developers Manual 12-37 12.6.7.8 Transmit Short Packet (TSP) 447 12.6.8 UDC Interrupt Control Register 0 (UICR0)Table 12-18. UDC Endpoint x Control Status Register, Where x is 5, 10, or 15 12.6.8.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7 448 12.6.9 UDC Interrupt Control Register 1 (UICR1)450 12.6.10 UDC Status/Interrupt Register 0 (USIR0)12.6.10.1 Endpoint 0 Interrupt Request (IR0) 12.6.10.2 Endpoint 1 Interrupt Request (IR1) 12.6.10.3 Endpoint 2 Interrupt Request (IR2) 12.6.10.4 Endpoint 3 Interrupt Request (IR3) 12.6.10.5 Endpoint 4 Interrupt Request (IR4) 12.6.10.6 Endpoint 5 Interrupt Request (IR5) 12.6.10.7 Endpoint 6 Interrupt Request (IR6) 12.6.10.8 Endpoint 7 Interrupt Request (IR7) 451 12.6.11 UDC Status/Interrupt Register 1 (USIR1)12.6.11.1 Endpoint 8 Interrupt Request (IR8) 453 12.6.12 UDC Frame Number High Register (UFNHR)12.6.12.1 UDC Frame Number MSB (FNMSB) 12.6.12.2 Isochronous Packet Error Endpoint 4 (IPE4) 454 12.6.12.3 Isochronous Packet Error Endpoint 9 (IPE9)12.6.12.4 Isochronous Packet Error Endpoint 14 (IPE14) 12.6.12.5 Start of Frame Interrupt Mask (SIM) 12.6.12.6 Start of Frame Interrupt Request (SIR) 455 12.6.13 UDC Frame Number L ow Register (UFNLR )12.6.14 UDC Byte Count Register x (UBCRx), Where x is 2, 4, 7, 9, 12, or 14.12.6.14.1 Endpoint x Byte Count (BC[7:0]) 456 12.6.15 UDC Endpoint 0 Data Register (UDDR0)457 12.6.16 UDC Data Register x (UDDRx), Where x is 1, 6, or 11458 12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or 1212.6.18 UDC Data Register x (UDDRx), Where x is 3, 8, or 13 459 12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, or 1412.6.20 UDC Data Register x (UDDRx), Where x is 5, 10, or 1512-50 Intel PXA26x Processor Family Developers Manual 460 12.6.21 UDC Register Locations463 AC97 Controller Unit 13497 Inter-Integrated Circuit Sound Controller 14513 MultiMediaCard Controller 15549 Network/Audio Synchronous Serial Protocol Serial Ports 16585 Hardware UART 17617 Internal Flash 18
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