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| Download Write Command Buffer |
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Bits | 7 |
| 6 |
| 5 | 4 |
| 3 | 2 | 1 | 0 | ||
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12 |
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| D (0x44) |
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13 |
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| A (0x41) |
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14 |
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| T (0x54) |
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15 |
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| E (0x45) |
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| Note |
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| • Byte 2 set to 0x00, |
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Multiple Update Firmware commands will generally be required to transfer the entire program image from the host to the FCR200 DRAM. When the last data block is transferred (mode
=0x07) the FCR200 terminates data transfer and performs a CRC checksum on data received.
It is required that the FC initiator sends from the beginning of the firmware image to the end. No out of sequence Write Buffers are allowed.
If the CRC test is successful, the Controller will reboot. The FCR200 will use the newly updated firmware. If the CRC test fails, the image transferred to DRAM is discarded, and the controller continues to use the previous firmware image.
It is required that the Parameter list length be the same as the FCP_DL field in the FCP_CMND IU.
•Bytes
•The mode will be set to 0x06 for the first & middle Write Buffers and 0x07 for the last.