Cypress CYV15G0404DXB Txratea, Txrateb, Txratec, Txrated, Rfena, Rfenb, Rfenc, Rfend, Rxpllpda

		CYV15G0404DXB
Table 9. Device Configuration and Control Latch Descriptions (continued)
Name	Signal Description
TXRATEA	Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to select
TXRATEB	the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the associated
TXRATEC	REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx output clocks
TXRATED	are full rate clocks and follow the frequency and duty cycle of the associated REFCLKx± input. When
	TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by 20 to generate the serial
	bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the REFCLKx±
	input. When TXCKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using both the rising
	and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx is LOW, is an invalid state and this combination
	is reserved.
RFENA	Reframe Enable. The initialization value of the RFENx latch = 1. RFENx selects if the receiver framer is
RFENB	enabled or disabled. When RFENx = 1, the associated channel’s framer is enabled to frame per the presently
RFENC	enabled framing mode and selected framing character. When RFENx = 0, the associated channel’s framer is
RFEND	disabled, and no received bits alters the frame offset.
RXPLLPDA	Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the
RXPLLPDB	associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated PLL and
RXPLLPDC	analog circuitry is powered-down. When RXPLLPDx = 1, the associated PLL and analog circuitry is enabled.
RXPLLPDD
RXBISTA	Receive Bist Disabled. The initialization value of the RXBISTx latch = 1. RXBISTx selects if receive BIST is
RXBISTB	disabled or enabled. When RXBISTx = 1, the receiver BIST function is disabled. When RXBISTx = 0, the
RXBISTC	receive BIST function is enabled.
RXBISTD
TXBISTA	Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit BIST
TXBISTB	is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0, the
TXBISTC	transmit BIST function is enabled.
TXBISTD
OE2A	Secondary Differential Serial Data Output Driver Enable. The initialization value of the OE2x latch = 0.
OE2B	OE2x selects if the OUT2± secondary differential output drivers are enabled or disabled. When OE2x = 1, the
OE2C	associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When
OE2D	OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration
	interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this
	disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET
	sampled LOW) disables all output drivers.
OE1A	Primary Differential Serial Data Output Driver Enable. The initialization value of the OE1x latch = 0. OE1x
OE1B	selects if the OUT1± primary differential output drivers are enabled or disabled. When OE1x = 1, the associated
OE1C	serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When OE1x = 0,
OE1D	the associated serial data output driver is disabled. When a driver is disabled via the configuration interface,
	it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled
	state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled
	LOW) disables all output drivers.
PABRSTA	Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The
PABRSTB	PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is
PABRSTC	written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized. PABRST
PABRSTD	is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal clock domain.
	PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the initialization of
	the Phase Alignment Buffer.
GLEN[11..0]	Global Enable. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
	channels simultaneously in applications where several channels may have the same configuration. When
	GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When GLENx
	= 0 for a given address, that address is disabled from participating in a global configuration.
FGLEN[2..0]	Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a GLobal
	ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global channel,
	FGLEN forces the global update of the target latch banks.

Document #: 38-02097 Rev. *B Page 22 of 44

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