CYV15G0404DXB
CYV15G0404DXB AC Electrical Characteristics (continued)
Parameter | Description |
| Min. | Max | Unit |
tRISE[20] | CML Output Rise Time 20−80% (CML Test Load) | SPDSELx = HIGH | 60 | 270 | ps |
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| SPDSELx = MID | 100 | 500 | ps |
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| SPDSELx =LOW | 180 | 1000 | ps |
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tFALL[20] | CML Output Fall Time 80−20% (CML Test Load) | SPDSELx = HIGH | 60 | 270 | ps |
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| SPDSELx = MID | 100 | 500 | ps |
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| SPDSELx =LOW | 180 | 1000 | ps |
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tDJ [20, 29, 31] | Deterministic Jitter | IEEE 802.3z |
| 27 | ps |
Z [20, 30, 31] | Random Jitter (σ)[32] | IEEE 802.3z |
| 11 | ps |
RJ |
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tREFJ[20] | REFCLKx jitter tolerance / Phase noise limits |
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| TBD |
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tTXLOCK | Transmit PLLx lock to REFCLKx± |
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| 200 | μs |
CYV15G0404DXB | Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range |
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tRXLOCK | Receive PLL lock to input data stream (cold start) |
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| 376k | UI |
| Receive PLL lock to input data stream |
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| 376k | UI |
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tRXUNLOCK | Receive PLL Unlock Rate |
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| 46 | UI |
tJTOL[20] | Total Jitter Tolerance[32] | IEEE 802.3z | 600 |
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tDJTOL[20] | Deterministic Jitter Tolerance[32] | IEEE 802.3z | 370 |
| ps |
Capacitance[20]
Parameter | Description | Test Conditions | Max. | Unit |
CINTTL | TTL Input Capacitance | TA = 25°C, f0 = 1 MHz, VCC = 3.3V | 7 | pF |
CINPECL | PECL input Capacitance | TA = 25°C, f0 = 1 MHz, VCC = 3.3V | 4 | pF |
CYV15G0404DXB HOTLink II Transmitter Switching Waveforms
Transmit Interface
Write Timing
TXCLKx selected
TXCLKx
TXDx[7:0],
TXCTx[1:0],
Transmit Interface
Write Timing
REFCLKx selected
TXRATEx = 0
REFCLKx
TXDx[7:0],
TXCTx[1:0],
| tTXCLK |
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tTXCLKH | tTXCLKL |
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| tTXDS | tTXDH |
tREFCLK
tREFH tREFL
tTREFDS |
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Document #: | Page 30 of 44 |
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