Manuals / Cypress / Computer Equipment / Clock

Cypress manual Capacitance20, CYV15G0404DXB HOTLink II Transmitter Switching Waveforms

Models: CYV15G0404DXB

1 44

Download 44 pages 58.08 Kb

Page 30

Capacitance[20]

CYV15G0404DXB

CYV15G0404DXB AC Electrical Characteristics (continued)

Parameter	Description		Min.	Max	Unit
tRISE[20]	CML Output Rise Time 20−80% (CML Test Load)	SPDSELx = HIGH	60	270	ps
		SPDSELx = MID	100	500	ps

		SPDSELx =LOW	180	1000	ps

tFALL[20]	CML Output Fall Time 80−20% (CML Test Load)	SPDSELx = HIGH	60	270	ps
		SPDSELx = MID	100	500	ps

		SPDSELx =LOW	180	1000	ps

tDJ [20, 29, 31]	Deterministic Jitter (peak-peak)[32]	IEEE 802.3z		27	ps
Z [20, 30, 31]	Random Jitter (σ)[32]	IEEE 802.3z		11	ps
RJ
tREFJ[20]	REFCLKx jitter tolerance / Phase noise limits			TBD
tTXLOCK	Transmit PLLx lock to REFCLKx±			200	μs
CYV15G0404DXB	Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range
tRXLOCK	Receive PLL lock to input data stream (cold start)			376k	UI
	Receive PLL lock to input data stream			376k	UI

tRXUNLOCK	Receive PLL Unlock Rate			46	UI
tJTOL[20]	Total Jitter Tolerance[32]	IEEE 802.3z	600		ps
tDJTOL[20]	Deterministic Jitter Tolerance[32]	IEEE 802.3z	370		ps

Capacitance[20]

Parameter	Description	Test Conditions	Max.	Unit
CINTTL	TTL Input Capacitance	TA = 25°C, f0 = 1 MHz, VCC = 3.3V	7	pF
CINPECL	PECL input Capacitance	TA = 25°C, f0 = 1 MHz, VCC = 3.3V	4	pF

CYV15G0404DXB HOTLink II Transmitter Switching Waveforms

Transmit Interface

Write Timing

TXCLKx selected

TXCLKx

TXDx[7:0],

TXCTx[1:0],

Transmit Interface

Write Timing

REFCLKx selected

TXRATEx = 0

REFCLKx

TXDx[7:0],

TXCTx[1:0],

	tTXCLK
tTXCLKH	tTXCLKL
	tTXDS	tTXDH

tREFCLK

tREFH tREFL

tTREFDS						t


						TREFDH

Document #: 38-02097 Rev. *B

Page 30 of 44

[+] Feedback

Image 30

Cypress manual Capacitance20, CYV15G0404DXB HOTLink II Transmitter Switching Waveforms

Contents

Functional Description FeaturesCYV15G0404DXB Independent Clock Quad HOTLink II Transceiver with ReclockerElasticity CYV15G0404DXB Transceiver Logic Block DiagramPhase AlignTransmit Path Block Diagram Phase-Align BufferCYV15G0404DXB Boundary CYV15G0404DXBJTAG ScanCYV15G0404DXB Device Configuration and Control Block= Internal Signal + FeedbackPin Configuration Top View CYV15G0404DXBPin Configuration Bottom View CYV15G0404DXBSignal Description Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverI/O Characteristics Transmit Path Data and Status SignalsPin Definitions continued CYV15G0404DXB Quad HOTLink II Transceiver CYV15G0404DXBReceive Path Data CYV15G0404DXB Pin Definitions continued CYV15G0404DXB Quad HOTLink II TransceiverPage 10 of Configuration Latches CYV15G0404DXBPin Definitions continued CYV15G0404DXB Quad HOTLink II Transceiver CYV15G0404DXB Transmit Data Path Phase Align BufferCYV15G0404DXB HOTLink II Operation Input RegisterSignal Name EncoderData Encoding CYV15G0404DXBTransmit PLL Clock Multiplier Transmit BISTTransmit Modes Encoder BypassSerial Output Drivers Signal Detect/Link FaultTransmit Channels Enabled CYV15G0404DXB Receive Data PathReclocker Clock/Data RecoveryReceive Channel Enabled Deserializer/FramerFramer 10B/8B Decoder BlockReceive BIST Operation CYV15G0404DXBOutput Bus Power ControlDevice Reset State Receive Elasticity BufferBIST Status State Machine Device Configuration and Control InterfaceReceive Status Bits CYV15G0404DXBMask Function Global Enable FunctionForce Global Enable Function Latch TypesCYV15G0404DXB Page 21 ofCYV15G0404DXB Page 22 ofTable 10. Device Control Latch Configuration Table Device Configuration StrategyJTAG Support CYV15G0404DXBCYV15G0404DXB 3-Level Select InputsJTAG ID Receive Character Status BitsCYV15G0404DXB Figure 2. Receive BIST State MachineMaximum Ratings CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Operating RangeCYV15G0404DXB DC Electrical Characteristics continued AC Test Loads and WaveformsCYV15G0404DXB CYV15G0404DXB AC Electrical Characteristics Transmitter LVTTL Switching Characteristics Over the Operating RangeCYV15G0404DXB JTAG Test Clock Characteristics Over the Operating Range CYV15G0404DXB AC Electrical Characteristics continuedBus Configuration Write Timing Characteristics Over the RESETTransmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 CYV15G0404DXB AC Electrical Characteristics continuedWrite Timing CYV15G0404DXB HOTLink II Transmitter Switching Waveforms continuedTransmit Interface REFCLKx selectedCYV15G0404DXB Switching Waveforms for the CYV15G0404DXB HOTLink II ReceiverReceive Interface Read Timing Recovered Clock selected RXRATEx = Receive Interface Read Timing REFCLKx Selected full rate RXCLKx±WREN ADDR30DATA70 Switching Waveforms for the CYV15G0404DXB HOTLink II ReceiverCYV15G0404DXB CYV15G0404DXB 8B/10B Transmission Code X3.230 Codes and Notation ConventionsNotation Conventions Transmission OrderUse of the Tables for Generating Transmission Characters CYV15G0404DXBDIN or QOUT CYV15G0404DXB Page 38 ofCYV15G0404DXB Valid Data Characters TXCTx0 = 0, RXSTx20 = 000 continuedPage 39 of CYV15G0404DXB Page 40 ofCYV15G0404DXB Page 41 ofK28.7 41 CYV15G0404DXBK28.5 41 Running DisparityCYV15G0404DXB Package DiagramOrdering Information + FeedbackDocument History Page ISSUECYV15G0404DXB Document Number