Pin Configuration Bottom View | Cypress CYV15G0404DXB specification

CYV15G0404DXB

Pin Configuration (Bottom View)

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

OUT

IN

OUT

IN

VCC

OUT

IN

GND

OUT

IN

OUT

IN

GND

OUT

IN

VCC

OUT

IN

OUT

IN

B2–

B2–

B1–

B1–

A2–

A2–

A1–

A1–

D2–

D2–

D1–

D1–

C2–

C2–

C1–

C1–

B

OUT

IN

OUT

IN

VCC

OUT

IN

GND

OUT

IN

OUT

IN

GND

OUT

IN

VCC

OUT

IN

OUT

IN

B2+

B2+

B1+

B1+

A2+

A2+

A1+

A1+

D2+

D2+

D1+

D1+

C2+

2+

C1+

C1+

TDO

LP

LDTD

VCC

SPD

RCLK

GND

DATA

DATA

DATA

DATA

GND

VCC

IN

IN

TMS

TDI

C

TRST

ULCC

ULCD

END

EN

SELD

ENB

[1]

[3]

[5]

[7]

SELB

SELC

TMEN3

SCAN

VCC

LP

VCC

LP

GND

DATA

DATA

DATA

DATA

GND

SPD

VCC

IN

IN

TCLK

D

ULCB

ULCA

RESET

EN2

ENA

ENB

[0]

[2]

[4]

[6]

SELC

SELA

SELD

E

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

F

RX

TX

RX

RCLK

RCLK

TX

RX

Rx

STB[0]

CLKOB

STB[1]

ENA

END

DC[0]

DC[7]

DC[6]

RX

SPD

LP

SPD

TX

TX

TX

G

WREN

DB[1]

SELA

ENC

SELB

DC[1]

DC[4]

DC[7]

H

GND

GND

GND

GND

GND

GND

GND

GND

J

RX

RX

RX

RX

TX

TX

TX

TX

DB[2]

DB[5]

DB[0]

STB[2]

DC[3]

DC[2]

DC[5]

CTC[1]

RX

RX

RX

TX

TX

REF

RX

K

LFIB

DB[7]

DB[4]

DB[3]

CLKC

CTC[0]

CLKC–

DC[2]

TX

RX

RX

RX

TX

REF

RX

L

LFIC

DB[6]

CLKB–

CLKB+

DB[6]

DC[6]

CLKC+

DC[3]

M

TX

TX

REF

REF

TX

RCLK

RX

RX

CLKB

ERRB

CLKB–

CLKB+

ERRC

ENC

DC[5]

DC[4]

N

GND

GND

GND

GND

GND

GND

GND

GND

P

TX

TX

TX

TX

RX

RX

RX

RX

DB[2]

DB[3]

DB[4]

DB[5]

STC[1]

STC[0]

DC[0]

DC[1]

R

TX

TX

TX

TX

RX

RX

TX

RX

DB[7]

CTB[1]

DB[0]

DB[1]

CLKC–

CLKC+

CLKOC

STC[2]

T

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U

RX

RX

TX

RX

VCC

TX

TX

GND

TX

REF

ADDR

TXC

GND

RX

RX

VCC

TX

TX

TX

TX

STA[1]

STA[2]

CTB[0]

DA[2]

CTA[0]

DA[4]

DA[1]

CLKD–

[0]

TA[1]

DD[1]

DD[2]

CTD[1]

DD[2]

DD[1]

DD[0]

V

RX

RX

RX

RX

VCC

TX

TX

GND

TX

REF

ADDR

RX

GND

RX

RX

VCC

RX

TX

TX

TX

STA[0]

DA[0]

DA[3]

DA[7]

DA[7]

DA[3]

CLKOA

CLKD+

[2]

STD[2]

STD[0]

DD[3]

DD[6]

CTD[0]

DD[4]

DD[3]

RX

RX

REF

TX

TX

TX

RX

ADDR

ADDR

RX

RX

RX

TX

TX

W

LFIA

VCC

GND

GND

VCC

LFID

DA[1]

DA[4]

CLKA+

DA[6]

DA[2]

ERRA

CLKA+

[1]

[3]

STD[1]

DD[4]

CLKD–

DD[7]

DD[5]

Y

RX

RX

REF

TX

VCC

TX

TX

GND

RX

TX

NC[1]

TX

GND

RX

RX

VCC

RX

RX

TX

TX

DA[5]

DA[6]

CLKA–

ERRD

DA[5]

DA[0]

CLKA–

CLKA

CLKOD

DD[0]

DD[5]

CLKD+

DD[7]

CLKD

DD[6]

Note

1. NC=Do Not Connect

Document #: 38-02097 Rev. *B

Page 7 of 44

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Image 7

Cypress CYV15G0404DXB manual Pin Configuration Bottom View

Contents

Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block Diagram Phase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock Signals Device Control Signals Name Characteristics Signal DescriptionStatus Signals Receive Path Clock Signals Use Local Clock . When Reframe Mode Select Link Fault Indication OutputDevice Configuration and Control Bus Signals Control Write Enable . CYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II Operation Data Encoding Encoder Transmit Modes Transmit BistTransmit PLL Clock Multiplier Serial Line Receivers Signal Detect/Link FaultSerial Output Drivers CYV15G0404DXB Receive Data Path Reclocker Clock/Data RecoveryDeserializer/Framer Framer 10B/8B Decoder BlockReceive Bist Operation Bits Detected Receive Elasticity Buffer Power ControlDevice Reset State Output Bus DECBYPx = Decbyp = Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name Decoder Bypass Mode Signal Name Bus Weight Bit Name Name Signal Description Device Configuration and Control Latch Descriptions Rxckseld RxckselaRxckselb Rxckselc Txrated TxrateaTxrateb Txratec Jtag Support Device Configuration StrategyDevice Control Latch Configuration Table Required step Receive Elasticity buffer underrun/overrun Running disparity error . The character onLevel Select Inputs Normal character received . The valid Data RX PLL Bistdatacompare 000 / BistcommandcompareBisterror Biststart Operating Range CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Maximum Ratings Lvttl Output Test Load18 Power Supply TypAC Test Loads and Waveforms CML Output Test Load Parameter Description Min Max Unit CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating REFCLKx Switching Characteristics Over the Operating Range Device Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range Transmit Serial Outputs and TX PLL Characteristics Over Parameter Description Test Conditions Max Unit CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Transmit Interface Write Timing REFCLKx selected TXRATEx = TXCTx10 Transmit InterfaceWrite Timing REFCLKx selected TXDx70 REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Lvttl in PU VCC PowerReset Lvttl in PU CML RXDC4 Lvttl OUT RXDC7 Lvttl OUTTXDB6 Lvttl TXDC0 Lvttl Transmission Order X3.230 Codes and Notation ConventionsNotation Conventions 8B/10B Transmission Code Hex Value Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Valid Transmission Characters Data Byte Name Abcdei fghj Abcdei fghj Name Data Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern CYV15G0404DXB-BGI Package DiagramOrdering Information CYV15G0404DXB-BGC Methods to implement it New Data SheetAGT UKK/VED