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Cypress manual Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver, + Feedback

Models: CYV15G0404DXB

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CYV15G0404DXB

Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver

Receive Interface Read Timing REFCLKx Selected full rate RXCLKx±

REFCLKx

RXDx[7:0],

RXSTx[2:0],

TXERRx[36]

RXCLKx

tREFCLK

tREFH tREFL

tRREFDA

tRREFDW

tREFxDV+

tREFxDV–

tRREFDW

Notes

34.The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLKx±.

35.The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input.

36.TXERRx is synchronous to RXCLKx only when RXCLKx is selected as REFCLK.

Receive Interface Read Timing REFCLKx Selected half rate RXCLKx±

REFCLKx

RXDx[7:0], RXSTx[2:0],

TXERRx[36]

tREFH

tRREFDA

tREFCLK tREFL

tRREFDA tRREFDW

tRREFDW

tREFxDV+					tREFxDV–

RXCLKx

Note 37

Receive Interface Read Timing Recovered Clock selected RXRATEx = 0

RXCLKx+

RXCLKx-

RXDx[7:0],

RXSTx[2:0],

tRXCLKP

tRXDV–

tRXDV+

Document #: 38-02097 Rev. *B

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Cypress manual Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver, + Feedback

Contents

Features CYV15G0404DXBFunctional Description Independent Clock Quad HOTLink II Transceiver with ReclockerCYV15G0404DXB Transceiver Logic Block Diagram PhaseElasticity AlignCYV15G0404DXB Transmit Path Block DiagramPhase-Align Buffer CYV15G0404DXB JTAGBoundary ScanDevice Configuration and Control Block = Internal SignalCYV15G0404DXB + FeedbackPin Configuration Top View CYV15G0404DXBPin Configuration Bottom View CYV15G0404DXBPin Definitions CYV15G0404DXB Quad HOTLink II Transceiver I/O CharacteristicsSignal Description Transmit Path Data and Status SignalsReceive Path Data Pin Definitions continued CYV15G0404DXB Quad HOTLink II TransceiverCYV15G0404DXB Page 10 of CYV15G0404DXBPin Definitions continued CYV15G0404DXB Quad HOTLink II Transceiver Pin Definitions continued CYV15G0404DXB Quad HOTLink II Transceiver Configuration LatchesCYV15G0404DXB Phase Align Buffer CYV15G0404DXB HOTLink II OperationCYV15G0404DXB Transmit Data Path Input RegisterEncoder Data EncodingSignal Name CYV15G0404DXBTransmit BIST Transmit ModesTransmit PLL Clock Multiplier Encoder BypassSignal Detect/Link Fault Transmit Channels EnabledSerial Output Drivers CYV15G0404DXB Receive Data PathClock/Data Recovery Receive Channel EnabledReclocker Deserializer/Framer10B/8B Decoder Block Receive BIST OperationFramer CYV15G0404DXBPower Control Device Reset StateOutput Bus Receive Elasticity BufferDevice Configuration and Control Interface Receive Status BitsBIST Status State Machine CYV15G0404DXBGlobal Enable Function Force Global Enable FunctionMask Function Latch TypesCYV15G0404DXB Page 21 ofCYV15G0404DXB Page 22 ofDevice Configuration Strategy JTAG SupportTable 10. Device Control Latch Configuration Table CYV15G0404DXB3-Level Select Inputs JTAG IDCYV15G0404DXB Receive Character Status BitsCYV15G0404DXB Figure 2. Receive BIST State MachineCYV15G0404DXB DC Electrical Characteristics Power Up RequirementsMaximum Ratings Operating RangeCYV15G0404DXB CYV15G0404DXB DC Electrical Characteristics continuedAC Test Loads and Waveforms CYV15G0404DXB CYV15G0404DXB AC Electrical CharacteristicsTransmitter LVTTL Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical Characteristics continued Bus Configuration Write Timing Characteristics Over theJTAG Test Clock Characteristics Over the Operating Range RESETCYV15G0404DXB HOTLink II Transmitter Switching Waveforms Capacitance20Transmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB AC Electrical Characteristics continuedCYV15G0404DXB HOTLink II Transmitter Switching Waveforms continued Transmit InterfaceWrite Timing REFCLKx selectedSwitching Waveforms for the CYV15G0404DXB HOTLink II Receiver Receive Interface Read Timing Recovered Clock selected RXRATEx =CYV15G0404DXB Receive Interface Read Timing REFCLKx Selected full rate RXCLKx±ADDR30 DATA70WREN Switching Waveforms for the CYV15G0404DXB HOTLink II ReceiverCYV15G0404DXB CYV15G0404DXB X3.230 Codes and Notation Conventions Notation Conventions8B/10B Transmission Code Transmission OrderDIN or QOUT Use of the Tables for Generating Transmission CharactersCYV15G0404DXB CYV15G0404DXB Page 38 ofPage 39 of CYV15G0404DXBValid Data Characters TXCTx0 = 0, RXSTx20 = 000 continued CYV15G0404DXB Page 40 ofCYV15G0404DXB Page 41 ofCYV15G0404DXB K28.5 41K28.7 41 Running DisparityPackage Diagram Ordering InformationCYV15G0404DXB + FeedbackISSUE CYV15G0404DXBDocument History Page Document Number