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Cypress CYV15G0404DXB manual Ordering Information, Package Diagram, + Feedback, 51-85123-*E

Models: CYV15G0404DXB

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CYV15G0404DXB

Ordering Information

Speed	Ordering Code	Package Name	Package Type	Operating
Speed	Ordering Code	Package Name	Package Type	Range
				Range
Standard	CYV15G0404DXB-BGC	BL256	256-Ball Thermally Enhanced Ball Grid Array	Commercial

Standard	CYV15G0404DXB-BGI	BL256	256-Ball Thermally Enhanced Ball Grid Array	Industrial

Package Diagram

256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256

51-85123-*E

Document #: 38-02097 Rev. *B

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Cypress CYV15G0404DXB manual Ordering Information, Package Diagram, + Feedback, 51-85123-*E

Contents

Independent Clock Quad HOTLink II Transceiver with Reclocker FeaturesCYV15G0404DXB Functional DescriptionAlign CYV15G0404DXB Transceiver Logic Block DiagramPhase ElasticityPhase-Align Buffer Transmit Path Block DiagramCYV15G0404DXB Scan CYV15G0404DXBJTAG Boundary+ Feedback Device Configuration and Control Block= Internal Signal CYV15G0404DXBCYV15G0404DXB Pin Configuration Top ViewCYV15G0404DXB Pin Configuration Bottom ViewTransmit Path Data and Status Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverI/O Characteristics Signal DescriptionCYV15G0404DXB Pin Definitions continued CYV15G0404DXB Quad HOTLink II TransceiverReceive Path Data Pin Definitions continued CYV15G0404DXB Quad HOTLink II Transceiver CYV15G0404DXBPage 10 of CYV15G0404DXB Configuration LatchesPin Definitions continued CYV15G0404DXB Quad HOTLink II Transceiver Input Register Phase Align BufferCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathCYV15G0404DXB EncoderData Encoding Signal NameEncoder Bypass Transmit BISTTransmit Modes Transmit PLL Clock MultiplierCYV15G0404DXB Receive Data Path Signal Detect/Link FaultTransmit Channels Enabled Serial Output DriversDeserializer/Framer Clock/Data RecoveryReceive Channel Enabled ReclockerCYV15G0404DXB 10B/8B Decoder BlockReceive BIST Operation FramerReceive Elasticity Buffer Power ControlDevice Reset State Output BusCYV15G0404DXB Device Configuration and Control InterfaceReceive Status Bits BIST Status State MachineLatch Types Global Enable FunctionForce Global Enable Function Mask FunctionPage 21 of CYV15G0404DXBPage 22 of CYV15G0404DXBCYV15G0404DXB Device Configuration StrategyJTAG Support Table 10. Device Control Latch Configuration TableReceive Character Status Bits 3-Level Select InputsJTAG ID CYV15G0404DXBFigure 2. Receive BIST State Machine CYV15G0404DXBOperating Range CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Maximum RatingsAC Test Loads and Waveforms CYV15G0404DXB DC Electrical Characteristics continuedCYV15G0404DXB Transmitter LVTTL Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical CharacteristicsCYV15G0404DXB RESET CYV15G0404DXB AC Electrical Characteristics continuedBus Configuration Write Timing Characteristics Over the JTAG Test Clock Characteristics Over the Operating RangeCYV15G0404DXB AC Electrical Characteristics continued CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Transmit Interface Write Timing REFCLKx selected TXRATEx =REFCLKx selected CYV15G0404DXB HOTLink II Transmitter Switching Waveforms continuedTransmit Interface Write TimingReceive Interface Read Timing REFCLKx Selected full rate RXCLKx± Switching Waveforms for the CYV15G0404DXB HOTLink II ReceiverReceive Interface Read Timing Recovered Clock selected RXRATEx = CYV15G0404DXBSwitching Waveforms for the CYV15G0404DXB HOTLink II Receiver ADDR30DATA70 WRENCYV15G0404DXB CYV15G0404DXB Transmission Order X3.230 Codes and Notation ConventionsNotation Conventions 8B/10B Transmission CodeCYV15G0404DXB Use of the Tables for Generating Transmission CharactersDIN or QOUT Page 38 of CYV15G0404DXBValid Data Characters TXCTx0 = 0, RXSTx20 = 000 continued CYV15G0404DXBPage 39 of Page 40 of CYV15G0404DXBPage 41 of CYV15G0404DXBRunning Disparity CYV15G0404DXBK28.5 41 K28.7 41+ Feedback Package DiagramOrdering Information CYV15G0404DXBDocument Number ISSUECYV15G0404DXB Document History Page