Cypress CYV15G0404DXB manual Jtag, Boundary, Scan, Controller

CYV15G0404DXB

Receive Path Block

SPDSELA

RXPLLPDA

RCLKENA

LPENA

INSELA

INA1+ INA1–

INA2+ INA2–

TXLBA

ULCA

SPDSELB

RECLCK[A..D] are Internal Reclocker Signals

TXLB[A..D] are Internal Serial Loopback Signals

							JTAG
						Boundary
		RECLCKA						Scan
						Controller
	Receive
	Signal
	Monitor
		Shifter	Framer	10B/8B BIST	Elasticity Buffer				Output Register
Recovery
	Clock &
	Data
	PLL

= Internal Signal

RESET

TRST

TMS

TCLK

TDI

TDO

LFIA

8RXDA[7:0]

3

RXSTA[2:0]

RXPLLPDB

RCLKENB

	Clock		RXCLKA+
RECLCKB	Select	⎟2	RXCLKA–

LPENB

INSELB

INB1+

INB1–

INB2+

INB2–

TXLBB

ULCB

Receive

Signal

Monitor

Clock &

Data

Recovery

PLL

Shifter Framer

10B/8B BIST

Elasticity Buffer

Output Register

LFIB

8RXDB[7:0]

3

RXSTB[2:0]

SPDSELC

RXPLLPDC

RCLKENC

RECLCKC	Clock			RXCLKB+
		⎟	2
	Select			RXCLKB–

LPENC

INSELC

INC1+

INC1–

INC2+

INC2–

TXLBC

ULCC

SPDSELD

Receive

Signal

Monitor

Clock &

Data

Recovery

PLL

Shifter Framer

10B/8B BIST

Elasticity Buffer

Output Register

LFIC

8RXDC[7:0]

3

RXSTC[2:0]

RXPLLPDD

RCLKEND

	Clock		RXCLKC+
RECLCKD	Select	⎟2	RXCLKC–

LPEND

INSELD

IND1+

IND1–

IND2+

IND2–

TXLBD

ULCD

Receive

Signal

Monitor

Clock &

Data

Recovery

PLL

Shifter Framer

10B/8B BIST

Elasticity Buffer

Output Register

LFID

8RXDD[7:0]

3

RXSTD[2:0]

SDASEL[A..D][1:0]

LDTDEN

Clock

Select

RFMODE[A..D][1:0]

RFEN[A..D]

FRAMCHAR[A..D]

DECMODE[A..D]

RXBIST[A..D]

RXCKSEL[A..D]

DECBYP[A..D]

RXRATE[A..D]

⎟2

RXCLKD+ RXCLKD–

Document #: 38-02097 Rev. *B

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