Pll | Cypress CYV15G0404DXB guide

CYV15G0404DXB

Receive Path Block

SPDSELA

RXPLLPDA

RCLKENA

LPENA

INSELA

INA1+ INA1–

INA2+ INA2–

TXLBA

ULCA

SPDSELB

RECLCK[A..D] are Internal Reclocker Signals

TXLB[A..D] are Internal Serial Loopback Signals

JTAG

Boundary

RECLCKA

Scan

Controller

Receive

Signal

Monitor

Shifter

Framer

10B/8B BIST

Elasticity Buffer

Output Register

Recovery

Clock &

Data

PLL

= Internal Signal

RESET

TRST

TMS

TCLK

TDI

TDO

LFIA

8RXDA[7:0]

3

RXSTA[2:0]

RXPLLPDB

RCLKENB

	Clock							RXCLKA+
RECLCKB	Select		⎟2					RXCLKA–
	Select							RXCLKA–

LPENB

INSELB

INB1+

INB1–

INB2+

INB2–

TXLBB

ULCB

Receive

Signal

Monitor

Clock &

Data

Recovery

PLL




				Shifter		Framer

10B/8B BIST

Elasticity Buffer

Output Register

LFIB

8RXDB[7:0]

3

RXSTB[2:0]

SPDSELC

RXPLLPDC

RCLKENC

RECLCKC	Clock								RXCLKB+
RECLCKC	Clock		⎟	2					RXCLKB+
	Select			2					RXCLKB–
	Select								RXCLKB–

LPENC

INSELC

INC1+

INC1–

INC2+

INC2–

TXLBC

ULCC

SPDSELD

Receive

Signal

Monitor

Clock &

Data

Recovery

PLL




				Shifter		Framer

10B/8B BIST

Elasticity Buffer

Output Register

LFIC

8RXDC[7:0]

3

RXSTC[2:0]

RXPLLPDD

RCLKEND

	Clock							RXCLKC+
RECLCKD	Select		⎟2					RXCLKC–
	Select							RXCLKC–

LPEND

INSELD

IND1+

IND1–

IND2+

IND2–

TXLBD

ULCD

Receive

Signal

Monitor

Clock &

Data

Recovery

PLL







				Shifter		Framer

10B/8B BIST

Elasticity Buffer

Output Register

LFID

8RXDD[7:0]

3

RXSTD[2:0]

SDASEL[A..D][1:0]

LDTDEN

Clock

Select

RFMODE[A..D][1:0]

RFEN[A..D]

FRAMCHAR[A..D]

DECMODE[A..D]

RXBIST[A..D]

RXCKSEL[A..D]

DECBYP[A..D]

RXRATE[A..D]

⎟2

RXCLKD+ RXCLKD–

Document #: 38-02097 Rev. *B

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Cypress CYV15G0404DXB manual Pll

Contents

Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer Phase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Name Characteristics Signal Description Status SignalsReceive Path Clock Signals Device Control Signals Use Local Clock . When Link Fault Indication Output Device Configuration and Control Bus SignalsControl Write Enable . Reframe Mode Select CYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data Path Encoder Data Encoding Transmit Modes Transmit BistTransmit PLL Clock Multiplier Signal Detect/Link Fault Serial Output DriversCYV15G0404DXB Receive Data Path Serial Line Receivers Reclocker Clock/Data RecoveryDeserializer/Framer 10B/8B Decoder Block Receive Bist OperationBits Detected Framer Power Control Device Reset StateOutput Bus Receive Elasticity Buffer Device Configuration and Control Interface Output Register Bit Assignments Signal NameDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp = Device Configuration and Control Latch Descriptions Name Signal Description Rxcksela RxckselbRxckselc Rxckseld Txratea TxratebTxratec Txrated Device Configuration Strategy Device Control Latch Configuration TableRequired step Jtag Support Running disparity error . The character on Level Select InputsNormal character received . The valid Data Receive Elasticity buffer underrun/overrun Bistdatacompare 000 / Bistcommandcompare BisterrorBiststart RX PLL CYV15G0404DXB DC Electrical Characteristics Power Up RequirementsMaximum Ratings Operating Range Power Supply Typ AC Test Loads and WaveformsCML Output Test Load Lvttl Output Test Load18 CYV15G0404DXB AC Electrical Characteristics Receiver Lvttl Switching Characteristics Over the OperatingREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max Unit Bus Configuration Write Timing Characteristics Over Jtag Test Clock Characteristics Over the Operating RangeTransmit Serial Outputs and TX PLL Characteristics Over Device CYV15G0404DXB HOTLink II Transmitter Switching Waveforms Capacitance20Transmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max Unit Transmit Interface Write Timing REFCLKx selectedTXDx70 TXCTx10 REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing VCC Power Reset Lvttl in PUCML Lvttl in PU RXDC7 Lvttl OUT TXDB6 LvttlTXDC0 Lvttl RXDC4 Lvttl OUT X3.230 Codes and Notation Conventions Notation Conventions8B/10B Transmission Code Transmission Order Code Violations Resulting from Prior Errors Use of the Tables for Generating Transmission CharactersValid Transmission Characters Data Byte Name Hex Value Abcdei fghj Name Abcdei fghj Data Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern Package Diagram Ordering InformationCYV15G0404DXB-BGC CYV15G0404DXB-BGI New Data Sheet AGTUKK/VED Methods to implement it