Cypress CYV15G0404DXB manual

CYV15G0404DXB

Table 14.	Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data	Bits	Current RD		−	Current RD+			Data	Bits		−	Current RD+
Byte	Bits	Current RD			Current RD+			Byte	Bits		Current RD	Current RD+
Name	HGF EDCBA	abcdei fghj			abcdei fghj			Name	HGF EDCBA		abcdei fghj	abcdei fghj
D0.4	100 00000	100111	0010		011000	1101		D0.5	101 00000		100111 1010	011000 1010
D1.4	100 00001	011101	0010		100010	1101		D1.5	101 00001		011101 1010	100010 1010
D2.4	100 00010	101101	0010		010010	1101		D2.5	101 00010		101101 1010	010010 1010
D3.4	100 00011	110001	1101		110001	0010		D3.5	101 00011		110001 1010	110001 1010
D4.4	100 00100	110101	0010		001010	1101		D4.5	101 00100		110101 1010	001010 1010
D5.4	100 00101	101001	1101		101001	0010		D5.5	101 00101		101001 1010	101001 1010
D6.4	100 00110	011001	1101		011001	0010		D6.5	101 00110		011001 1010	011001 1010
D7.4	100 00111	111000	1101		000111	0010		D7.5	101 00111		111000 1010	000111 1010
D8.4	100 01000	111001	0010		000110	1101		D8.5	101 01000		111001 1010	000110 1010
D9.4	100 01001	100101	1101		100101	0010		D9.5	101 01001		100101 1010	100101 1010
D10.4	100 01010	010101	1101		010101	0010		D10.5	101	01010	010101 1010	010101 1010
D11.4	100 01011	110100	1101		110100	0010		D11.5	101	01011	110100 1010	110100 1010
D12.4	100 01100	001101	1101		001101	0010		D12.5	101	01100	001101 1010	001101 1010
D13.4	100 01101	101100	1101		101100	0010		D13.5	101	01101	101100 1010	101100 1010
D14.4	100 01110	011100	1101		011100	0010		D14.5	101	01110	011100 1010	011100 1010
D15.4	100 01111	010111	0010		101000	1101		D15.5	101	01111	010111 1010	101000 1010
D16.4	100 10000	011011	0010		100100	1101		D16.5	101	10000	011011 1010	100100 1010
D17.4	100 10001	100011	1101		100011	0010		D17.5	101	10001	100011 1010	100011 1010
D18.4	100 10010	010011	1101		010011	0010		D18.5	101	10010	010011 1010	010011 1010
D19.4	100 10011	110010	1101		110010	0010		D19.5	101	10011	110010 1010	110010 1010
D20.4	100 10100	001011	1101		001011	0010		D20.5	101	10100	001011 1010	001011 1010
D21.4	100 10101	101010	1101		101010	0010		D21.5	101	10101	101010 1010	101010 1010
D22.4	100 10110	011010	1101		011010	0010		D22.5	101	10110	011010 1010	011010 1010
D23.4	100 10111	111010	0010		000101	1101		D23.5	101	10111	111010 1010	000101 1010
D24.4	100 11000	110011	0010		001100	1101		D24.5	101	11000	110011 1010	001100 1010
D25.4	100 11001	100110	1101		100110	0010		D25.5	101	11001	100110 1010	100110 1010
D26.4	100 11010	010110	1101		010110	0010		D26.5	101	11010	010110 1010	010110 1010
D27.4	100 11011	110110	0010		001001	1101		D27.5	101	11011	110110 1010	001001 1010
D28.4	100 11100	001110	1101		001110	0010		D28.5	101	11100	001110 1010	001110 1010
D29.4	100 11101	101110	0010		010001	1101		D29.5	101	11101	101110 1010	010001 1010
D30.4	100 11110	011110	0010		100001	1101		D30.5	101	11110	011110 1010	100001 1010
D31.4	100 11111	101011	0010		010100	1101		D31.5	101	11111	101011 1010	010100 1010
Document #: 38-02097 Rev. *B												Page 40 of 44

[+] Feedback

Image 40

Cypress CYV15G0404DXB manual

Contents

Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer Phase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Name Characteristics Signal Description Status SignalsReceive Path Clock Signals Device Control Signals Use Local Clock . When Link Fault Indication Output Device Configuration and Control Bus SignalsControl Write Enable . Reframe Mode Select CYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data Path Encoder Data Encoding Transmit Modes Transmit BistTransmit PLL Clock Multiplier Signal Detect/Link Fault Serial Output DriversCYV15G0404DXB Receive Data Path Serial Line Receivers Reclocker Clock/Data RecoveryDeserializer/Framer 10B/8B Decoder Block Receive Bist OperationBits Detected Framer Power Control Device Reset StateOutput Bus Receive Elasticity Buffer Device Configuration and Control Interface Output Register Bit Assignments Signal NameDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp = Device Configuration and Control Latch Descriptions Name Signal Description Rxcksela RxckselbRxckselc Rxckseld Txratea TxratebTxratec Txrated Device Configuration Strategy Device Control Latch Configuration TableRequired step Jtag Support Running disparity error . The character on Level Select InputsNormal character received . The valid Data Receive Elasticity buffer underrun/overrun Bistdatacompare 000 / Bistcommandcompare BisterrorBiststart RX PLL CYV15G0404DXB DC Electrical Characteristics Power Up RequirementsMaximum Ratings Operating Range Power Supply Typ AC Test Loads and WaveformsCML Output Test Load Lvttl Output Test Load18 CYV15G0404DXB AC Electrical Characteristics Receiver Lvttl Switching Characteristics Over the OperatingREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max Unit Bus Configuration Write Timing Characteristics Over Jtag Test Clock Characteristics Over the Operating RangeTransmit Serial Outputs and TX PLL Characteristics Over Device CYV15G0404DXB HOTLink II Transmitter Switching Waveforms Capacitance20Transmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max Unit Transmit Interface Write Timing REFCLKx selectedTXDx70 TXCTx10 REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing VCC Power Reset Lvttl in PUCML Lvttl in PU RXDC7 Lvttl OUT TXDB6 LvttlTXDC0 Lvttl RXDC4 Lvttl OUT X3.230 Codes and Notation Conventions Notation Conventions8B/10B Transmission Code Transmission Order Code Violations Resulting from Prior Errors Use of the Tables for Generating Transmission CharactersValid Transmission Characters Data Byte Name Hex Value Abcdei fghj Name Abcdei fghj Data Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern Package Diagram Ordering InformationCYV15G0404DXB-BGC CYV15G0404DXB-BGI New Data Sheet AGTUKK/VED Methods to implement it