![](/images/new-backgrounds/1172471/172471103x1.webp)
MIB DescriptioncgmControl
Table 5-4 cgmBitsTable (continued)
OID | MIB Object | Description | Access |
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.1.1.2.1.81 | bitsT1TraiCi | Transmit | r/w |
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| Setting this bit causes the ESF |
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| transmitted in the FDL bit position. |
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| Default value is (0). |
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.1.1.2.1.91 | bitsE1RxSyncC | Frame resynchronization criteria | r/w |
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| Default value is (0). |
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.1.1.2.1.112 | bitsT3ClkForce | When set to (1), it, forces the T3 clock output from | r/w |
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| the framer to be output to the PLL even if no signal |
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| is present. This should only be set for test purposes |
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| since the framer will generate a |
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| in the absence of a valid input. |
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| Default value is (0). |
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.1.1.2.1.113 | bitsT3ClkSquelch | When set to disabled (1), it forces the T3 output to | r/w |
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| the PLL to be active even if a loss of frame or an |
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| alarm condition exists. This would typically be |
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| disabled for normal operation and only be set for |
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| unframed operation. |
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| Default value is (0). |
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.1.1.2.1.114 | bitsTestPattern | An 8- or | r/w |
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| repeatedly output on T1E1 port when the test |
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| output is enabled. |
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| Applies to the following |
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| dsx1ESF |
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| dsx1D4 |
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| dsx1E1 |
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| dsx1E1CRCMF |
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| dsx1E1unframed |
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| Default value is (0). |
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.1.1.2.1.115 | bitsTestPatternLength | Determines whether a 8 bit (0) or 16 bit (1) test | r/w |
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| pattern is generated. |
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| Applies to the following |
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| dsx1ESF |
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| dsx1D4 |
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| dsx1E1 |
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| dsx1E1CRCMF |
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| dsx1E1unframed |
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| Default value is (0). |
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52 |
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