Model3490A

 

 

SectionIV

C L O C K

DATA

BUFFERS E M I T T E R

T I M I N G

 

COUNTER

FOLLOWER

COUNTER

 

L T CI

 

HJC 2

 

HTC4

 

HTC8

 

HTC 16

 

HTC32

D C B A

 

TO DISPLAYAND

 

DATA OUIPUT

 

STATECLOCK

O S C I L L A T O RF R E O U E N C YFOR

6 O H z L I N E 4 M H z

 

 

5 0 H z L I N E 3 . 3 3 3 M H 2

Figure4-8. Block Diagram,Clock and Counters.

is derived from a Clock Oscillator which drivesthe Data Counter, a Timing Counter, and the State Clock. The Clock Oscillator is a crystal-controlled multivibrator. The oscillator frequency is 4 MtIz in instruments de- signedfor 60 Hz line operation,and 3.333 MHz in units for 50 Hz operation. The oscillator output is divided by two beforebeingappliedto the Data Counter.

484. DataGounter.

4{5. The Data Counter is a hexdecadecounter containing six decade counters, six 4line latches, and output multiplexing. At the end of rundown, a Transfer pulse from the Transfer and Zero Detect logic transfers the count information in BCD form into the 4-line latches.Scansignalsfrom the Dsplay assemblycausethe BCD count information to be transferredto the Display digit by digit, beginningwith the least significant digit. The Data Counter accumulates clock pulses continuously until a Clear Data Counter signalis receivedfrom the logic Output Decoder.

486. Buffers

4€7. Inputs to the buffer amplifiersare two intermediate outputs from the Data Counter, Divide by 10,000 and Divide by 100,000.The outputs of theseamplifiers are gated by the Select Hundred Thousand Counts signals,HSHC and LSHC, from Logic Storage.If HSHC is HIGH and LSHC is LOW, the Divide by 100,000 output is selected,and if HSHC is LOW and LSHC is HIGH, the Divide by 10,000 output is selected.The Buffer output is appliedthrough an emitter follower to the Timing Counter.

4-88.TimingCounter.

4{9. The Timing Counterconsistsof a singleD flip-flop and a 4-bit binary counter. Five binary square wave sigrals are produced in addition to the Timing Counter input signal. This input signal is not a symmetrical $quarewave.but is HIGH for 9,000 (or 90,000) counts and LOW for I ,000(or 10,000)counts.Thesesix timing signalsgö to the QualifierMultiplexer, and are used to control run-up time, overload point, samplerate delay, and function delay.

 

NEXT.STATE

PRESENT

 

 

FUNCTION

STATE

 

INPUTS

COMBINATIONAL

COMBINATIONAL

 

 

LOGIC

 

 

OUTPUT

OUTPUTS

 

 

 

(GATES,RoM, etc.I

LOGIC

 

Figure4-9. Typical StateMachineBlock Diagram.

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