HP Car 3490A ;s,t3i5'/rp,ly,ffi, are, the, The, the, ing, ,1V, Stor, command, inhibit, one-shot, by a LOW, l3Ors--J, SectionIV, operation, a LOW true, "next-state

SectionIV

SAMPL € /HOLD TRIGGER

IHEHCI FROM

llrsHt FRoM ascrl

EXTEfrNAL

E X T E R N A L T B I G G E R E N A S L E (LXEN} FROM MEMORY STORAGE

STATECLOCKHSHC

LSHC INVERTED

STATE CLOCK

TOOUALIFIERMULTIPLEXER

Model3490A

DELAY SELECT LINES

IHOSA, HDSEI FROM

MEMORY STORAGE

TO OUALIFIEF

MULTIPLEXER

1 4 9 0 - 8 - 3 4 4 0

Figure4-28. Block Diagramof S/H Timingand TriggerCircuits.

50 Hz instruments.Two Sample/HoldState Clock signals which are oppositein phase,HSHC and LSHC, are

used to clock the State Storageand Memory Storage flip-flops. All six "next-state"signalsare clocked into

storageat the sametime. One-halfclock cyclelater, the Memory Storage flip-flops are clocked simultaneously. The clock signalto the Timing Counteris gatedby the Hold sigral from the Sample/Hold Trigger circuit.

4-232. Timing Counterand LevelTranslator.The Timing Counter is a l4-stagebinary counter/divider.Four outputs from this counter are applied to the kvel Translator, which converts the counter output logic levels to the 0 V to + 5 V levels used by subsequent circuits. Three outputs from the trvel Translatorarg. applied to the Delay Multiplexer and used in selecting the Acquire/Hold delay. The other two kvel Translator outputsgo to the QualifierMultiplexer.

4-233. Delay Multiplexer. Two Delay Selectlines from Memory Storage select the Delay Multiplexer output from its four input lines. If Track/Hold (no delay) operationis selected,the multiplexerselectsthe Sample/ Hold Trigger Circuit output and issues a Hold A commandimmediately.Whenoperatingin the Acquire/ Hold mode, the multiplexer output (Hold A) determines the length of delay between the receipt of a Hold command and the actual beginningof a Hold condition. The delay requiredis determinedby the rangeselected, and is related to the DC Amplifier gain, as shown in Table4-5.

4-23.Sample/HoldTriggerCircuits.Figure4-29shows the Sample/HoldTrigger timing sequenceAn. external Sample/HoldTrigger pulseis appliedto a pulse-stretch-

ing one-shotcircuit whose output is a positive pulse approx-rmately40 microsqcondsin width, calledExternal Hold H. This output may be inhibited by a LOW true inhibit sigral. LISH, from the ASCII option. Also, the Ertemal Hold H output must be enabled by a LOW Ertemal Triaeer Enable signalfrom the Mem'oryStor-

Table4-5. GainDelayRelationship.

Range	DC Amp	Delay Select		Nominal Delay (psl
	Gain	HDSEHDSA Option 060 Option 05t0
,1V.	xlOO	L	L	2048.8	2458.5
1 V	x l O	H	L	512.6	615 . 0
1 0 v	xl	L	H	128.4	154"0
100v	x l O	H	L	512 . 6	615.0
1000v	xl	L	H	124.4	154.O

*Measurement accuracy is not specified for the .1 V range. Operation on this range is not recommended due to the amount of Gaussian(thermal) noise present.

age. If these conditions are correct, this begins a Sample/Holdmeasurement.The External Hold H pulse. alsoenablesthe Clock Gate,allowingthe Clock signalto start the Timing Counter. After the measurementse- quence is begun, the Read Only Memory issuesan Internal Hold Command (through Memory Storage) which continues to enable the Clock Gate for the remainder of the measurement.At the same time, a sigral from the Memory Storage sets the External

EXTERNAL TRIGGER,
ENABLE LXEN	TRIGGERCOMMANDS
	I N H I B I T E D

EXTERNAL

;s,t3i5'/rp,ly,ffi

EXTERML HOLDH

HEHS

IN T E R N A L HOLD

COMMAND Hl3Ors--J

HI H C

Figure4-29. Sample/HoldTriggerTiming.

l - ' h