HP Car 3490A manual Model3490A Tl-90.AlgorithmicStateMachine, Block Diagram,Main LogicCircuits

Model3490A

tl-90.AlgorithmicStateMachine.

4-91. T\e 3490A main logic circuits employ a logic svstem called an Algorithmic State Machine (ASM)' Fizure 4-9shows a typical StateMachineblock diagram' nir nSU outputs are determined by the "state" of the machine at a given instant, called the "present state'" Certain outputs in the present state, along with one or more "qualifier" inputs, determinethe "next state" of the ASIr{. For example, if the qualifier input is a certain

timing signal, the Next State Function logic may wait until this qualifier reaches a predetermined level to changethe state of the ASM. Each new state provides a

different combination of outputs.

492.Figore 4-10 is a block diagramof the main logic ASM flow chart. This chart illustrates the process followed by the ASM in taking a normal measurement' Note that at many points, the path taken dependson the condition of a certain signal. This signal is the qualifier input to the ASM at that particular time.

4-93. State Clock. The input to the State Clock is the 4MlIz (or 3.333 MHz) output from the Clock Oscillator (Figure 4-8). This signal is divided by a 4-bit binary counter and a D flip-flop, so that the State Clock output has a period of 8 prs(or 9.6 ps). The two State Clock outputs, labeled HSCK and LSCK, are 180" out of phase, and are used for alternate synchronousclocking of input signals to the ASM storage. The State Clock output is also used in the Data Output and Remote Control circuits.

4-94. Read Only Memory. Figure +11 is a block diagram of the Main Ingic Circuits. The 3490A logic usesa Read Only Memory. Sevenof the memory inputs

Section IV

in the "present" state are used,alongwith a "Qualifier', input, to determine the next state. Five other memory outputs are used to select the qualifier, as well as to initiate the other logic action. In addition, the Read Only Memory (ROM) also supplies an Output Enable sipal to the Logic Output Decoder, a Memory Output sigrralto the Logic Storageflip-flops, Transfer Enable to the Transfer utd Zero Detect gates, and a Close Electronic Switch signalto the Integrator.

4-95. Present State Storage. The Present State Storage consists of seven D flip-flops. The next state outputs from the ROM are clocked into the flip-flops by the State Clock L signal. The D flip-flop outputs are the present state. Together with the qualifier input, they determine the next state outputs of the ROM. The qualifier input is clocked into memory storage at the ROM input by the State Clock H signal 4 ps later to preventuncertaintyin the ROM next statedecision.

4-96. State ldentification. Eachstate may be identified by a three-digitoctal coded number determinedby the levelsof D flip-flop outputs YMA throughYMG, shown in Figure 7-30. For example, in state 000, all seven outputs are LOW ("0"). If only YMA goesHIGH ("1"), the state is then 001. In the state where YMG= l; Y M F = 0 ; Y M E = l ; Y M D = 1 ; Y M C = l ; Y M B = l ; YMA = I (l 0l 1 I l1), the stateidentihcationnumber is

131.A total decimalnumber of 128 statesarepossible, with the higheststate identification number being 177-

4-97. Oualifier Multiplexer. A block diagram of the

Qualifier Multiplexer is shown in Figure 4-12. Qualifier EnablesignalsLMQA, LMQS, and LMQC from the ROM

are inverted and used to selectone output out of eight

Figure4-11. Block Diagram,Main LogicCircuits.

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