HP Car 3490A courPursl, +168.ShiftRegisters, 4166.lsolationAsembly, 4-160.DataMultiplexers, +158 .DATAOUTPUTOPTION021, 4-162Data.OutputSequentialLogic

SectionIV

4-152. lsolatedTriggerand Hold.

4-153. External Encode and Hold are both LOW true signals.They are inverted and applied through emitter followers to photo-isolators, consisting of a light- emitting diode which drives a photosensitivetransistor. Consequently,there is no electricalconnectionbetween outguard and inguard circuits.

It-l54.Sample/HoldTriggerCircuits.

4-155. Sample/HoldTrigger. Whenthis input goesfrom HIGH to LOW for a pulse width of at least 30 nanoseconds,it signalsthe Sample/Holdcircuits(Option

040)to "hold". This pulse is inverted twice and applied to an isolation transformer, which couples the trigger sigral to the inguard Sample/Hold circuits. The Sample/ Hold Trigger input connectionis direct coupled,and if the connection(rearpanelJ7 pin 9) is left open,+ 5 V is present at that pin. This trigger will not initiate a reading unless the StretchedPulseOutput is connectedexter- nally to ExternalEncode.

4-156. AC Trigger. This input may be any pulsehaving

anegative-goingleading edge of 2 to 15 volts and a width of at least 30 nanosecondsThis. pulseis capaci- tively coupled to the isolation transformer to trigger the Sample/Holdcircuits.

zt-157.StretchedPulseOut. This output changesfrom HIGH to LOW for at least 240 microsecondsfor each Sample/Holdor AC Trigger input. StretchedPulseOut may be connected to External Encode to initiate a measurementsimultaneouslywith the Sample/Holdtrig- ger.

+158 .DATAOUTPUTOPTION021 .

4-159. The Data Output connectionsat the rear panel are isolated from the internal circuits of the 3490^. Power for the outguard circuits is supplied by the outguard + 5 V power supply. Outguard ground is isolatedfrom inguardcircuit common and chassis(earth) ground, and may be floated up to 40 V abovechassis. Figure 7-32 is a diagramof the Data Output circuits.

4-160.DataMultiplexers.

4-161. Threemultiplexers,eachhaving8 input linesand

4output lines, are used to transfer the Data Output

information across the guard to four eight-bit shift registers.An "output select" (Ss) connection to each multiplexer selectsone set of four inputs if the Ss input is HIGH. and the other set of four inputs if Seis LOW.

The outputs from two multiplexersare applied to the inputs of the third, or "master" multiplexer. The

outputs of the mastermultiplexer are enabledfor only the eights periodsof time necessaryto transferall the Data Output information, as shown in Figure4-18. The SequentialLogic determinesthe time and sequenceof mlolTnationtransfer.

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Model34904

SEOUENTIALLOGICINPUTS

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Figure4-18. DataOutput Timing Diagram(Option 021).

4-162Data.OutputSequentialLogic.

zt-163.Figure 4-18 shows the timing sequenceof the sequential Logic inputs and outputs. The Logic is enabled when the End of Reading signal goes LOW at the completion of a measurement.The three scansignals which control the outputs from the Data Counter operate the Logic to correlate the multiplexer outputs with the outputs from the Data Counter. The Sequential Logic consistsbasically of three JK flipflops. The scan signal inputs to the flip-flops are gated to obtain the desiredoutput pattem.

4164. OataClock.

+165. A Frequency Doubler is used so that a clock pulse is issued for each transition of the Scan A signal. Thesepulsesare delayed slightly before being applied to the outguard Shift Registers, to allow time for the multiplexeroutputsto reachthe properstate.

4166.lsolationAsembly.

arl67. Eachsignalis transferredacrossguardthrough a photoisolator, which consistsof a light+mitting diode driving a photosensitivetransistor. Consequently,no electrical connection is made between the inguard and outguardcircuits.

+168.ShiftRegisters.

4-169. Four 8-bit Shift Registersareused,providingthe capability of 32 paralleloutput lines.Each time a Data Clock pulse is received, the information in the shift registershifts one position and a new input is accepted.

Adual-input Exclusive OR gate in each of the shift registerinput lines determineswhether the coded Data Output information is HIGH true or LOW true. The operationof thesegatesis suchthat if oneand only one input is HIGH the output is HIGH. If both inputs are