SectionIV

returns to LOW to indicate programmingis complete. While the signalis HIGH, it enablesgatesin both inguard and outguard circuits to allow transfer of information.

At the sametime, an output from the Sequentiall,ogic disables the State Clock signal to the t-ocal/Remote Flip-Flop, to prevent the clock from changing the flip-flop during a remote programmingperiod, Whenthe Program Flag signal is LOW, it disables the Scan A divide-by-two flip-fl op.

4186. DataClock.

+187. A Frequency Doubler is used so that a clock pulse is issued for each transition of the Scan A signal. These clock pulses are delayed slightly before being applied to the Shift Registers,to allow time for the programinformation to reachthe properstate.

+188.ShiftRegisters.

+189. One-half of the dual 4-bit shift registermicro- circuit carries the range information, and the other contains function information. Each Data Clock pulse shifts the information bits in the registersone position and inserts a new bit. The shift register outputs are appliedto two multiplexers.

41 90. Local/RemoteMultiplexers.

+191 . The four outputs from eachof thesemultiplex- ers may be either of two setsof four inputs. Onesetof four inputs is the remote programinformation bits, and

the other set is the correspondinginformation from the front panel switches. The logic level of the "output

select" connection to the multiplexer selectseither {he local or remote program information. The "outpüi

select" signal is the output of the Local/Remote Flip-Flop. The multiplexer outputs are the rangeand function informationusedin the logic circuits.

4-192. LocaURemoteFlip-Flop.

4-193. The Local/RemoteFlip-Flop providesthe "out- put select" signalto the Incal/Remote Multiplexers.A NOR gate is used to gate the State Clock input to the flip-flop. When the 3490A is turned on, the Turn-on L signal from the logic circuits sets the Local/Remote Flip-Flop to the local state. When the Remote Enable line at the rear panel connector is held LOW, a L,OW sigtal is applied to the D input of the flip-flop. A HIGH State Clock pulse then sets the Q output LOW. This LOW signal to the multiplexers selects the remote program information. An inverter connected to the other flip-flop output drivesthe Remote annunciatorin the display.

4194. DauFlag.

t195. The Data Flag output signalgoesHIGH at the begrnningof a measurementand LOW to indicate the readingsequencehas beencompleted.If the instrument

Model3490A

is operatingin the autorangemode, Data Flag remains HIGH until a reading on the correct range has been completed.

4 . 196GENERAL.PURPOSEINTERFACEBUSI/O(0PTtoN 030).

4-197. The GeneralPurposeInterface Bus I/O (GPIB) option permits the Model 3490A to operate on a single data/control bus with severalother instruments. The ASCII code, used in this system,is an eight-bif +2-l octal code, parallelbit, serialcharacter.The 3490A I/O has a talk addressand a listen address,which allowsthe controlling instrumentto instruct the 3490A to output measurementdata or to receiveprogramminginforma- tion. Since eachinstrument on the bus may haveits own distinct addresscodes, a single controller is able to instruct or receivedata from each one individually. The 3490A GPIB option is compatible with the -hp-9800 seriescalculators.

4-198GPIB.System.

4-199. A typical bus systemis shown in Figure4-20. A total of 15 instrumentsmay be connectedin parallelto the bus. Each instrument on the bus is assigred an address (or addresses)so that it can be selected individually by the controller. This enablesthe controller to determine which instruments will be communicating on the bus at ury given time. An instrument will havea listen addressif it canreceivedata,a talk address if it can output data,or both a listen and a talk address if it can both receiveand transmit data. For example, the listen addressfor the 3490A is normally the ASCII code character 6, and the normal talk addressis V, assignedasshownin Paragraph3-104.and Table3-6.

4-200. A principal advantageof the bus systemis that both remote programmingand data output are done on

3490A

9820AD V M CALCULATOR

( C O N T R O L L E R }(TALKER}

( L I S T E N E R I

1 2 f t . M A X .

A S C I I 8 U S C A B L E S

F R E O U E N C Y

COUNTERPRINTER

(TALKER}( L I S T E N E R }

( L I S T E N E R I

Figure4-20. Typical BusSystem.

+10