HP Car 3490A manual 228Sample/Hold.LogicCircuits, +25, Flgure4-27. Sample/HoldLogic Block Diagram

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Offset Amplifier output) and appliesthis voltage to the Integrator (A - to - D Conversion)circuit through Kl, as shown in Figure 4-31. If Sample/Holdoperation is not selected,th9 DC Input Amplifier output signalby-passes the Sample/Hold circuits through K2.

4-228Sample/Hold.LogicCircuits.

4-229. Fipre 44,7 is a block diagramof the Sample/ Hold logic circuits. The function of each block is discussedin the following paragraphs.The sequenceof

the main timing signalsmust be modified for Sample/

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Amplifier is shorted, and its output is only the offset present. This offset voltage is inverted by the Offset Amplifier and subtracted from the Sample/Hold sigral voltage at the input to the S/H Output Amplifier. The purposg ald action of the Offset Amplifier are also mentioned in Paragraph4-220.

4-227. Output Amplifier. This unity-gain inverting amplifier inverts the output from Circuit B (less the

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timing also grounds the input to the DC Input Amplifier during the run-up and run-down peri- ods. The Sample/Hold logic circuits also determine the proper delay for Acquire/Hold measurementsin accor- dance with the range selected. The logic circuits are controlled by an Algorithmic State Machine (ASM). A brief explanation of an ASM will be found in paragraph 4-90.

4-290.Timing and TriggerCircuits. The block diagam in Figure4-28 detailsthe circuitsand sigralsusedin the timing and trigger circuits.

4-231. Sample/Hold State Clock. The input to the Sample/HoldState Clock comesfrom the 34904 crvs- tal-controlled Clock Oscillator, A1U3. This signal is divided by 16, so that the Sample/Hold State Clock sigral has a frequency of 250 kHz in instruments desigred for 60 Hz line operation, and 208.3 kHz in

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Flgure4-27. Sample/HoldLogic Block Diagram.

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