SectionIV

ENAELE

IN P U T S

ENABLE

OUALIFIERINPUT

TO ROM

Figure4-12. BlockDiagram,QualifierMultiplexer.

input signalsto eachof three3-to-8line decodersThese. three outputs are applied simultaneously to the AND/ OR Invert Gate. The other two QualifierEnablesigrals, I-il,IQD and LMQE, are inverted and both HIGH and LOW true signalsareusedat the AND/OR Invert Gateto select one of the three decoder outputs. The output from the Invert Gate is applied to a D flip-flop, which is clocked by State Clock signalHSCK, and whoseoutput is the Qualifier Input to the ROM. This clock signalis 180" out of phasewith StateClock LSCKwhich clocks the Present State Storageflip-flops. This preventsuncer- tainty in the ROM next statedecision.

4-98. Logic Output Decoder.This 4-to-l6line decoder usesfour inverted enablesignalsfrom ROM, HMQA-D, to select the proper output. In addition, the Output Enable signal from the ROM, and the State Clock signal LSCK must both be LOW to obtain an output from the." decoder.All outputs from this decoderare LOW true, and are used to clock the Logic Storage flip-flops, to clear certain storageflip-flops, to clear the Data and Timing Counters,to operatethe RangeCounter, and to clock the'Polarityand Overloadstorageflip-flops.

4-99. Logic Storage.The input levelto the D inputs of the six Logic Storage flip-flops is determined by the inverted Memory Output signal from the ROM. Each flip-flop is clocked to changeits output at a different time (or times)duringthe measurementsequence.

4-100. Main Timing Flip-Flops.ThreeMain Timing Bits are producedby Logic Storageflip-flops.All of theseare used in controlling the DC Switching Logic, which determinesinputs to and gainof the DC Amplifier. Main Timing Bit A is also used to drive the sample rate indicator. WhenMain Timing Bit B is LOW, it activates the Auto Zero circuits in the DC Amplifier and Integrator.

tl-101.End of ReadingFlip-Flop.The output of this tlip-t1opis normally HIGH, and goesLOW shortly after the Zero Detect of a measurementIf. the instrumentis Ln the autorange mode, the End of Reading sigral

Model3490A

remainsHIGH until after Zerc Detect on the correct range.After going LOW, End of ReadinggoesHIGH at the end of the measurementsequence.The HIGH to LOW transition signalsto the Data Output circuits that the information storedin the Data Counteris valid and

allowsthe data to be transferredacrossguardbeforethe Data Flaggoesfrom "busy'to "ready."

4-1O2. Data Flag Flip-Flop. The DataFlagoutput from this flip-flop goes LOW at the beginning of a measurement and remains LOW until the reading cycle is completed.If autorangeis selected,Data Flag remains LOW until a readinghasbeenmadeon the correctrange. This signal is inverted in both the Data Output and Remotecircuits.

4-103. Select Divide by 100,000 Flip-Flop. The two outputs from this flip-flop are used to select either the divide by 100,000 or divide by 10,000 counts output from the DataCounterto the Timing Counter.

4-104. Turn-OnClear. The output of the Turn-OnClear circuit is LOW for approximately 100 ms after the instrumentis tumed on. This LOW signalclearsthe Main Timing B and C flipflops and the PresentState Storage flip-flops, to force the logic into the preferred state when the instrument is first turned on.

4-105Input.PolarityStorage.

4-106. The input to this D flip-flop is the inverted output of the Analog Zero Detect Amplifier in the lntegratorcircuits.The flip-flop is clockedat the end of run-up. If the 34904 input is positive, the flip-flop D input will be LOW at the end of run-up, and HIGH if the input is negative.Both outputsareusedin the logic Zero Detect circuits. The output which goes to the Display and the DC Switching LoSc is HIGH for + input and LOW for - input.

4-107.TransferandZeroDetect.

4108. The Transferand Zerc Detectcircuitsareshown in the upper right hand corner of Figure 7-30. Two outputs are derived from these circuits; a LOW true Transfer signal, and a HIGH trve Zerc Detect sigtal. These signalsmay be issuedat end of run-down (when Integrator output reacheszerc), at overloadif readingis greater than 120 % of nnge, or when a False Transfer signal is given during Logic Test. Transfer goes to the Data Counter to transfer the count into the six quad latch circuits in the countet.Zero Detectis one input to the Qualifier Multiplexer, indicatingto the ROM that a measurementhasbeencomPleted.

4-109. Overload.A Transfer Enable signal from the ROM goesHIGH at the start of run-down,and remains HIGH until after the Transfer sigral goes LOW. This enable signal is applied to one input of each of three AND gatesin the AND/OR Invert Gate.The other input to the two-input AND gate is connectedto the Time