HP Car 3490A manual Too, Sample/HoldAnalogCircuits, +23, @ n z, P L I F IRE a

Model3490A

4:220. Waveforms shown in Figure 4-31 illustrate the measurement sequence for a single measurementon a sine wave, and the accompanyingnotations indicate the events occurring during the measurementsequence'In Sample/Hold measurements,the circuits must be in the Traci Mode from the completion of one measurement until the receipt of the next Sample/Hold Trigger command. For this reason'the DC Input Amplifier is connected to the input terminals during this entire period, and the normal auto-zero cycle of this amplifier iatrnot be used. Consequently, there is a slight offset voltagepresentin its output. This offset is-removedfrom the Sample/Holdmeasurementvoltage asfollows:

a.The voltage at point 6 (refer to the diagramand waveforms in Figure 4-31) during the run-up period,

3T4, is the algebraicsum of the voltagesat points 4 and S. nre voltage at point 4 is the sum of the input signal

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Section IV

held by the Sample/Hold circuits and the offset of the Input Amplifier. The voltage at point 5 during the same period is the inverse of the offset voltage. Ideally, then, the voltage at point 6 is equal to the input signalheld by the Sample/Holdcircuits (V4 + V5 = input signal).

b.During run-down, when the referencevoltage is held by the Sample/Hold circuits, the same condition exists. The voltagesat points 4 and 5 add, removing the Input Amplifier'soffset from the voltage at point 6.

&221.Sample/HoldAnalogCircuits.

4-222. Circuit A. Figure 424 contuns a simplified diagramof Sample/Hold Circuit A and a discussionof its operation.

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a.In the Track Mode,Sl is open,52 and 53 areclosed.The circuit from point A to point D operatesasan invertingunity€ain amplifier. This circuit consistsof a non-invertingamplifier with a gain of 4 betweenpoints B and C, followed by an integrating amplifier between points C and D. Very small blas currents are required by the FET source-followersin the input stageof the integrator.

b.For each nar level of output voltage at point D, current flows through 52 to readjustthe \roltageacrossthe integrator capacitorto the appropriae level. When a Hold A command is received,52 opensand no more current is suppliedto chang€the \toltageacrossthe capacitor, ln this Hold Mode,the voltageat point D remainsconstantwhile a measurementis complEted.

c.When the Hold comnrandoccurs,the gate voltageon the FET switch52 goesrcgatiw,causinga current to flow through the

iunction capacitanceof this FET. This current alters the \roltageon the integrator capacitor. Compensationfor this effect is providedby 53, which altersthe voltageon its associatedcapacitorat the other input to the amplifier in a similar fashion.

d.Sl is closedduringthe Hold Mode.Thislimits the amountof voltagechangeat point C, and preventscurrentsgoingfrom C to E throughany straycapacitanceor throughthe internalcapacitanceof FET switch52 duringthe Hold Mode.

Figure4-24. SimplifiedDiagramand Operationof S/H Circuit A.

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