HP Car 3490A manual

Model3490A

Trigger Enable signal HIGH, inhibiting any further Sample/Hold Trigger pulses for the duration of the measurement sequence. A measurement may also be initiated internally by the Intemal Hold Commandsignal if the 3490A is operating in the automatic sampling mode, or if triggeredby the front panel pushbutton.

+235. Read Only Memory. A microcircuit ReadOnly Memory (ROM) is the central component of the

Sample/Hold Logic control circuits. Six memory inputs in the "present" state, alongwith two "qualifier" inputs,

determine the next state of the ROM. In eachstate,the ROM provides the proper outputs to determinethe next step to be taken in the Sample/Hold measurement sequence.

+236. State and Memory Storage. The State Storage circuits are clearedwhen the 3490A is first tumed on. so that all six of the State Storageoutputs are LOW. Two of the next state outputs are stored in D Flip-Flops which are clocked by the positive-going edge of the clock signal, HSHC. The other four next state outputs are stored in a selectableinput storage unit, which is clocked by the negative-goingedgeofthe invertedclock sigral, LSHC. Consequently,all six ROM next state outputs are clocked into storage at the same time, becauseHSHC and LSHC are opposite in phase.The two qualifier inputs, as well as the control signal outputs from the ROM, are clocked into memory storageby the negative-goingedge of the clock signal, HSHC. By this method, all state storagecircuits are clocked at one time, and all memory storage circuits are clocked at another time.

4-23!. Oualifier Multiplexers. The two qualifier inputs t9 the ROM, along with the six present-stateinputs, determine the next-state outputs from the ROM. These qualifier inputs are selected by two 8line to lline multiplexers. Selection is determined bv three of the

SectionIV

present-stateoutputs from State StorageFIPA,HpB and HPC.

ut-238.Sample/Hold MeasurementSequence.The tim- ing sequencefor a Sample/Hold measurementis shown in Figure 4-30. The statesof Main Time Bits C, B and A must be modified for Sample/Hold measurementsin order for the circuits to track the input voltagebetween measurements.The statesof thesesignalsfor the various portions of the measurement cycle are shown in the upper part of Figure 4-30. The statesshown for a normal measurement(not Sample/Hold) are the statesof these signalsasreceivedby the Sample/Holdlogic circuits. The state sequencefor a Sample/Hold measurementis then modified as shown. During a normal measurement(with Sample/Hold in the 3490A), the timing bit sequenceis not modified; however, there is a delay in the Storage circuit equal to the duration of one cycle of the Sample/HoldStateClock.

zl-239.ReferencePolarity Logic. In Sample/Holdmea- surements, the 3490A input signal is inverted in the Sample/Holdamplifiers.Consequently,the polarity in- formation derived from the Integrator is incorrect. The logic level of the polarity signal must be inverted to supply the correct display polarity and to select the proper reference voltage for run-down. This is accom- plished by an Exclusive OR gate and an inverter. The gateoutput is HIGH if one and only one of its inputs is HIGH. If both inputs are either HIGH or LOW, the output is LOW. In Sample/Hold measurements,one input to the gate is alwaysLOW, so its output follows the polarity signal at the other input. The gateoutput is then inverted and becomesthe Display Polarity signal. When Sample/Holdoperationis not selected,one input to the Exclusive OR gate is not always HIGH. The polarity signal at the other input is then inverted by both the gate and the inverter;consequently,the logic level of the Display Polarity signal is the same as the

..Ratio Polaritysignalat the gateinput.

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