HP UX 11i v1 I/O Cards manual Data.setportsc.ptcfg-ptinfo.subchb.tmsl, Rti

ZCOM C I/F Library Routines

ZCONFIG (3X)

data.setportsc.ptcfg->ptinfo.subchb.tmsl[ ]

Timeslot assignment array: used for actions ZcDSC_ALL_PARMS or ZcDSC_SET_TIMESLOTS only. Up to 32 timeslot assignments are allowed. Each element of the array is indexed by the timeslot number. That is, timeslot 0 is in tmsl[0], timeslot 1 is in tmsl[1], etc. For action ZcDSC_ALL_PARMS, all timeslots are configured. For action ZcDSC_SET_TIMESLOTS only timeslot entries with the UPD bit set are configured. The timeslot definition for each element in the array is shown below:

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	UPD	TTI	Transmit subch number					Transmit fill mask
Set to 0		RTI	Receive subch number					Receive fill mask

UPD: The Update bit is used with the ZcDSC_SET_TIMESLOTS action to identify timeslots which are to be configured. Timeslots with the UPD bit not set, are unaffected by the ZcDSC_SET_TIMESLOTS action.

Detailed descriptions of the TTI, RTI, Transmit and Receive subchannel numbers, and the Transmit or Receive fill masks, can be found in the Siemens MUNICH32 data sheet in Section 4.2.4 Time Slot Assignment.

A TTI (Transmit Timeslot Inhibit) bit value of ‘1’ causes the transmit timeslot to be placed into tristate. The data is not destroyed but sent in the next non-tristated timeslot allocated to this subchannel.

A RTI (Receive Timeslot Inhibit) bit value of ‘1’ causes all data received in this timeslot to be ignored. The subchannel does not process inbound data for this timeslot.

The Rxcv and Txmit subch nmber fields associate the specified subchannel number with the Transmit and Receive timeslot, respectively. That is, tmsl[3] is used to specify which subchannel(s) will be using timeslot 3 for transmitting and receiving data. Note that they normally are, but are not required to be the same subchannel number for receiving and transmitting.

The fill mask is used to indicate which bits of the transmit and receive timeslot holds data.

200 Chapter 4