Intel 315889-002 manual 2Output Voltage Requirements, 2.1Voltage and Current - REQUIRED

Output Voltage Requirements

2Output Voltage Requirements

2.1Voltage and Current - REQUIRED

There will be independent selectable voltage identification (VID) codes for the core voltage regulator. The VID code is provided by the processor to the VRM/EVRDs, which will determine a reference output voltage, as described in Section 3.2. As previously mentioned, the VR 11.0 controller will support two VID tables:

1.An extended 7-bit VR 10.x table, ranging from 0.83125 V to 1.6 V

2.An 8-bit VR11.0 linear table ranging from 0.03125 V to 1.6 V (usable range 0.5 V- 1.6 V).

For Dual-Core Intel Xeon Processor 7000/7100/7200/5000/5100/5200 Series -based servers and Quad-Core Intel Xeon Processor 7300/5300/5400 Series -based servers/ workstations, the VID bits utilization will be as shown in the table below. Section 2.2 and Section 2.3 specify deviations from the VID reference voltage.

Table 2-1.	Processor VID signal implementation
		VID Signals used
	Processor Supported	by Processor and	Notes
		routed to VR with
		Pull-Up resistors
	Dual-Core Intel® Xeon®	VID[4:0,5]	VR10.2 mode; VID6 is not driven on the processor
	Processor 7000/7100 Series	(VID4=MSB	package (socket 604), but should be routed on the VR
	processor		side with a pullup resistor; VR’s VID7 to be pulled
		VID5=LSB)
			Low.
	Dual-Core Intel® Xeon®	VID[4:0,5]	VR10.2 mode; Land AM5 (equivalent to platform
	Processor 5000 Series	(VID4=MSB	signal VID6) is not driven on the processor package,
			but still routed to VID6 on VR side with a pullup
		VID5=LSB)
			resistor; VR’s VID7 to be pulled Low.
	Dual-Core Intel® Xeon®		VR11.0 mode; Land AM2 (equivalent to platform
	Processor 5100 Series, Quad-		signal VID0) is connected to VSS on the processor
	Core Intel® Xeon® Processor		package, and routed to VID0 on VR side with a pullup
	5300 Series, Dual-Core	VID[6:1]	resistor; VR’s VID7 to be pulled Low.
	Intel® Xeon® Processor
	5200 Series, or Quad-Core
	Intel® Xeon® Processor
	5400 Series processors
	Quad-Core Intel(R) Xeon(R)		VR11.0 mode; VID0 is not driven on the processor
	Processor 7300 Series &	VID[6:1]	package (socket 604P), but should be routed on the
	Dual-Core Intel(R) Xeon(R)		VR side and pulled Low; VR’s VID7 to be pulled Low.
	Processor 7200 Series
	processors

The load line tolerance in Section 2.2 shows the relationship between Vcc and Icc at the die of the processor.

The VRM/EVRD 11.0 is required to support the following:

•A maximum continuous load current (ICCTDC) of 130 A.

•A maximum load current (ICCMAX) of 150 A peak.

•A maximum load current step (ICCSTEP), within a 1 µs period, of 100 A.

•A maximum current slew rate (dICC/dt) of 1200 A/µs at the lands of the processor.

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