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Intel 315889-002 manual Figures, Tables

Models: 315889-002

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	8.10	Safety - PROPOSED	46
9	Manufacturing Considerations		47
	9.1	Lead Free (Pb Free)	47
A	Z(f) Constant Output Impedance Design		49
	A.1	Introduction - PROPOSED	49
	A.2	Voltage Transient Tool (VTT) Z(f) Theory	52
	A.3	VTT Z(f) Measurement Method	53
	A.4	Results	53
	A.5	Output Decoupling Design Procedure	56

Figures

2-1	VRM/EVRD 11.0 Load Current vs. Time	12
2-2	Processor Vcc Overshoot Example Waveform	16
2-3	Power Distribution Impedance vs. Frequency	17
2-4	Power-On Sequence Timing Diagram	19
2-5	Processor Transition States	21
2-6	Dynamic VID Transition States Illustration	21
2-7	Six-layerDual-Core Intel Xeon Processor-Based Server Platform VccP
	Power Delivery Impedance Model Path with 1206 Size Caps	23
2-8	Eight-layerDual-Core Intel Xeon Processor-Based Server Platform VccP
	Power Delivery Impedance Model Path with 1206 Size Caps	23
2-9	Eight-layerDual-Core Intel Xeon Processor-Based Server Platform VccP
	Power Delivery Impedance Model Path with 0805 Size Caps	23
2-10	Dual-Core Intel Xeon 5000 Series with Intel 5400 Chipsets Platform VccP
	Power Delivery Impedance Model Path - Example	25
3-1	Remote Sense Routing example	30
6-1	VRM 11.0 and Platform Present Detection	39
7-1	VRM 11.0 Pin Assignments	43
7-1	VRM 11.0 Module and Connector	44
A-1	Typical Intel® Microprocessor Voltage Regulator Validation Setup	49
A-2	Z(f) Network Plot with 1.25 mW Load Line	50
A-3	Time Domain Response of a Microprocessor Voltage Regulator	51
A-4	Time Domain Responses and Corresponding Fourier Spectra
	of Voltage, Current and Impedance	53
A-5	Photo of Motherboard Analyzed Showing High Frequency
	MLCC Capacitors In the Socket Cavity and Bulk Capacitors	54
A-6	Measured Platform Impedance Profile Showing Change
	in Impedance as Capacitors Are Removed	55
A-7	Designations of MLCC Cavity Capacitor Banks	55
A-8	Simulated and Measured Waveforms of Platform Impedance Profile	56

Tables

1-1 VRM/EVRD 11.0 Supported Platforms and Processors		............................................... 9
1-2	Guideline Categories	10
2-1 Processor VID signal implementation		11
2-2	Icc Guidelines	13
2-3 VID_Select, LL1, LL0 Codes		14
2-4	Impedance ZLL Measurement Parameter Limits	18
2-5	Startup Sequence Timing Parameters	19

4	315889-002

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Intel 315889-002 manual Figures, Tables

Contents

Voltage Regulator Module VRM and Enterprise Voltage Regulator-DownEVRDDesign Guidelines April315889-002 Contents ApplicationsFigures TablesHighest SKU Processors - Summary Revision History Rev #Description Rev. DateProject Document State RevisionProjects Covered Page 1Applications 1.1Introduction and TerminologyTable 1-2.Guideline Categories 2Output Voltage Requirements 2.1Voltage and Current - REQUIREDSustained Current A Time Duration sTable 2-2.Icc Guidelines 2.2Load Line Definitions - REQUIREDOutput Voltage Requirements Table 2-3.VID Select, LL1, LL0 Codes Sheet 1 of 2.3Voltage Tolerance - REQUIRED Table 2-3.VID Select, LL1, LL0 Codes Sheet 2 of2.4Processor VCC Overshoot - REQUIRED 2.5Impedance vs. Frequency - EXPECTEDZtarget = Z LL VR BW500 kHz 700 kHz2.7Processor Power Sequencing - REQUIRED 2.6Stability - REQUIREDVBOOT=1.1V PWM Vcc5V/12V VTT VTT PWRGD OUTEN VID SELECT Tg2.8Dynamic Voltage Identification D-VID REQUIRED Figure 2-5.Processor Transition States 2.9Overshoot at Turn-Onor Turn-Off- REQUIRED 2.10Output Filter Capacitance - REQUIREDFigure Figure Figure 6 layers, 2 power, 2 ground, 2 signal, 1 oz Cu Motherboard Socket & Package2.11Shut-DownResponse - REQUIRED 3.1Output Enable OUTEN - REQUIRED 3Control Signals3.2Voltage Identification VID 6 0 - REQUIRED Control Signals 315889-0023.3Differential Remote Sense VO SEN+ REQUIRED Socket Table 3-5.LL0, LL1, VID Select Specifications 3.4Load Line Select LL0, LL1, VID Select REQUIREDTable 3-6.VID Bit Mapping Control Signals 4Input Voltage and Current 4.1Input Voltages - EXPECTED4.2Load Transient Effects on Input Current EXPECTEDInput Voltage and Current 5.1Over-VoltageProtection OVP - EXPECTED 5Processor Voltage Output Protection5.2Over-CurrentProtection OCP - EXPECTED Processor Voltage Output Protection 6.1Voltage Regulator Ready VR Ready - REQUIRED 6Output Indicators6.2Voltage Regulator Hot VR hot# - PROPOSED 6.3Load Indicator Output Load Current PROPOSED 6.4VRM Present VRM pres# - EXPECTED6.5VR Identification VR ID# - EXPECTED Table 6-3.VRM pres# SpecificationsOutput Indicators VRM Pres#Output Indicators 7.1VRM Connector - EXPECTED 7.2VRM Tyco/Elcon Connector Keying7.2.1Connector Keying 7.2.2Connector Pin 1 OrientationTable 7-2.VRM 11.0 Connector Pin Descriptions VRM - Mechanical GuidelinesName Type7.4Mechanical Dimensions - PROPOSED 7.4.1Gold Finger SpecificationFigure 7-1.VRM 11.0 Module and Connector PCB Footprint8.1Operating Temperature - PROPOSED 8.2VRM Board Temperature - REQUIRED8.3Non-OperatingTemperature - PROPOSED 8Environmental Conditions8.10Safety - PROPOSED 8.5Altitude - PROPOSED8.6Electrostatic Discharge - PROPOSED 8.7Shock and Vibration - PROPOSED9Manufacturing Considerations 9.1Lead Free Pb FreeManufacturing Considerations A.1 Introduction - PROPOSED AZf Constant Output Impedance DesignFigure A-2.Zf Network Plot with 1.25 mΩ Load Line Page A.2 Voltage Transient Tool VTT Zf Theory Z f = FFT V t FFT I tA.3 VTT Zf Measurement Method A.4 ResultsPage 10uF 22uF A.5 Output Decoupling Design Procedure