Intel 315889-002 manual Socket

Control Signals

Figure 3-1. Remote Sense Routing example.

		High Impedance Path
		1k	1%
LGA 771	Socket	VCC_ DIE_ SENSE2
		Pin AL8
			10	1%
		VSS_ DIE_ SENSE2
		Pin AL7	10	1%
1 of 9	In µP				VCC/	VSS Feedback
10µF	Cavity	VCC_ DIE_ SENSE				Inputs
		Pin AN3
			10	1%
					EVRD11.0		Controller or
		VSS_ DIE_ SENSE
		Pin AN4	10	1%	VRM 11.0		Connector
		High Impedance Path
		1k	1%

Notes: For each processor, refer to the appropriate platform design guide (PDG) for the recommended VR’s remote sense routing.

The sense lines should be routed based on the following guidelines:

•Route differentially with a maximum of 5 mils separation.

•Traces should be at least 25 mils thick, but may be reduced when routed through the processor pin field.

•Traces should have the same length.

•Traces should not exceed 5 inches in length and should not violate pulse-width modulation (PWM) vendor length requirements.

•Traces should be routed at least 20 mils away from other signals.

•Each sense line should include a 0 – 100 Ω, 5% series resistor that is placed close to the PWM or VRM connector in order to filter noise from the power planes. Designers should consult with their power delivery solution vendor to determine the appropriate resistor value.

•Reference a solid ground plane.

•Avoid switching layers.

On a VRM, the positive sense line will be connected to VO_SEN+ and the negative sense line will be connected to VO_SEN–.

The processor VCC_DIE_SENSE, VSS_DIE_SENSE, VCC_DIE_SENSE2 and VSS_DIE_SENSE2 pins

should be connected to test points on the baseboard in order to probe the die voltage. These test points should be as close to the socket pins as possible.

A high impedance path (100X) should be routed to the center of the processor socket and terminated to one of the nine 10 µF capacitors. This provision serves as a precautionary regulation point, in the event the EVRD/VRM is powered on and processor is installed.

30 315889-002