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Intel 315889-002 manual 4Input Voltage and Current, 4.1Input Voltages - EXPECTED, Expected

Models: 315889-002

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4Input Voltage and Current

Input Voltage and Current

4Input Voltage and Current

4.1Input Voltages - EXPECTED

The power source for the VRM/EVRD is 12 V +5% / –8%. This voltage is supplied by a separate power supply. For input voltages outside the normal operating range, the VRM/EVRD should either operate properly or shut down.

4.2Load Transient Effects on Input Current -

EXPECTED

The design of the VRM/EVRD, including the input power delivery filter, must ensure that the maximum slew rate of the input current does not exceed 0.5 A/µs, or as specified by the separate power supply.

Note: In the case of a VRM design, the input power delivery filter may be located either on the VRM or on the baseboard. The decision for the placement of the filter will need to be coordinated between the baseboard and VRM designers.

It is recommended that the bulk input decoupling (with optional series 0.1-1 µH inductor) be placed on the baseboard by the VRM input connector and high frequency decoupling on the VRM module. Expected baseboard decoupling should be between 1000 µF to 2240 µF depending on VRM design and system power supply.

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315889-002

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Intel 315889-002 4Input Voltage and Current, 4.1Input Voltages - EXPECTED, 4.2Load Transient Effects on Input Current

Contents

VRM and Enterprise Voltage Regulator-DownEVRD Voltage Regulator ModuleDesign Guidelines April315889-002 Applications ContentsTables FiguresHighest SKU Processors - Summary Rev # Revision HistoryDescription Rev. DateRevision Project Document StateProjects Covered Page 1.1Introduction and Terminology 1ApplicationsTable 1-2.Guideline Categories 2.1Voltage and Current - REQUIRED 2Output Voltage RequirementsTime Duration s Sustained Current A2.2Load Line Definitions - REQUIRED Table 2-2.Icc GuidelinesOutput Voltage Requirements Table 2-3.VID Select, LL1, LL0 Codes Sheet 1 of Table 2-3.VID Select, LL1, LL0 Codes Sheet 2 of 2.3Voltage Tolerance - REQUIRED2.5Impedance vs. Frequency - EXPECTED 2.4Processor VCC Overshoot - REQUIREDVR BW Ztarget = Z LL500 kHz 700 kHz2.6Stability - REQUIRED 2.7Processor Power Sequencing - REQUIREDPWM Vcc VBOOT=1.1V5V/12V VTT VTT PWRGD OUTEN VID SELECT Tg2.8Dynamic Voltage Identification D-VID REQUIRED Figure 2-5.Processor Transition States 2.10Output Filter Capacitance - REQUIRED 2.9Overshoot at Turn-Onor Turn-Off- REQUIREDFigure Figure Figure 6 layers, 2 power, 2 ground, 2 signal, 1 oz Cu Socket & Package Motherboard2.11Shut-DownResponse - REQUIRED 3Control Signals 3.1Output Enable OUTEN - REQUIRED3.2Voltage Identification VID 6 0 - REQUIRED 315889-002 Control Signals3.3Differential Remote Sense VO SEN+ REQUIRED Socket 3.4Load Line Select LL0, LL1, VID Select REQUIRED Table 3-5.LL0, LL1, VID Select SpecificationsTable 3-6.VID Bit Mapping Control Signals 4.1Input Voltages - EXPECTED 4Input Voltage and Current4.2Load Transient Effects on Input Current EXPECTEDInput Voltage and Current 5Processor Voltage Output Protection 5.1Over-VoltageProtection OVP - EXPECTED5.2Over-CurrentProtection OCP - EXPECTED Processor Voltage Output Protection 6Output Indicators 6.1Voltage Regulator Ready VR Ready - REQUIRED6.2Voltage Regulator Hot VR hot# - PROPOSED 6.4VRM Present VRM pres# - EXPECTED 6.3Load Indicator Output Load Current PROPOSED6.5VR Identification VR ID# - EXPECTED Table 6-3.VRM pres# SpecificationsVRM Pres# Output IndicatorsOutput Indicators 7.2VRM Tyco/Elcon Connector Keying 7.1VRM Connector - EXPECTED7.2.1Connector Keying 7.2.2Connector Pin 1 OrientationVRM - Mechanical Guidelines Table 7-2.VRM 11.0 Connector Pin DescriptionsName Type7.4.1Gold Finger Specification 7.4Mechanical Dimensions - PROPOSEDPCB Footprint Figure 7-1.VRM 11.0 Module and Connector8.2VRM Board Temperature - REQUIRED 8.1Operating Temperature - PROPOSED8.3Non-OperatingTemperature - PROPOSED 8Environmental Conditions8.5Altitude - PROPOSED 8.10Safety - PROPOSED8.6Electrostatic Discharge - PROPOSED 8.7Shock and Vibration - PROPOSED9.1Lead Free Pb Free 9Manufacturing ConsiderationsManufacturing Considerations AZf Constant Output Impedance Design A.1 Introduction - PROPOSEDFigure A-2.Zf Network Plot with 1.25 mΩ Load Line Page Z f = FFT V t FFT I t A.2 Voltage Transient Tool VTT Zf TheoryA.4 Results A.3 VTT Zf Measurement MethodPage 10uF 22uF A.5 Output Decoupling Design Procedure