Output Voltage Requirements
2.4Processor VCC Overshoot - REQUIRED
The VRM/EVRD 11.0 is permitted short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a
20 MHz preference).
•VOS_MAX = Maximum overshoot voltage above VID = 50 mV
•TOS_MAX = Maximum overshoot time duration above VID = 25 µs
Figure
VID + 0.050 |
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Voltage [V] |
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VID - 0.000 |
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0 | 5 | 10 | 15 | 20 | 25 |
Time [us]
TOS: Overshoot time above VID
VOS: Overshoot voltage above VID
2.5Impedance vs. Frequency - EXPECTED
Vcc power delivery designs can be susceptible to resonance phenomena capable of creating droop amplitudes that violate the load line specification. This is due to the frequency varied PCB, output decoupling and socket impedances from the power plane layout structures. Furthermore, these resonances may not be detected through standard time domain validation and require engineering analysis to identify and resolve.
Impedance vs. Frequency, Z(f) performance simulations of the power delivery network is a strongly recommended method to identify and resolve these impedances, in addition to meeting the time domain load line in Section 2.2 and Section 2.3. The decoupling selection needs to be analyzed to ensure that the impedance of the decoupling is below the load line target up to the FBREAK (2 MHz) frequency as defined in Figure
16 |