Manuals / Intel / Household Appliance / Thermostat

Intel 315889-002 manual 2.11Shut-DownResponse - REQUIRED

Models: 315889-002

1 56

Download 56 pages 18.09 Kb

Page 26

2.11Shut-Down Response - REQUIRED

Output Voltage Requirements

2.11Shut-Down Response - REQUIRED

Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until power is cycled. If the extended VR 10 VID table is selected, the VRM/EVRD should turn off its output if VID [6:0] = XX11111. If the VR 11.0 VID table is selected, there are four VID off states; VID [6:0] = 0000000, 0000001, 1111110, or 1111111.

§

26	315889-002

Image 26

Intel 315889-002 manual 2.11Shut-DownResponse - REQUIRED

Contents

Design Guidelines Voltage Regulator ModuleVRM and Enterprise Voltage Regulator-DownEVRD April315889-002 Contents ApplicationsFigures TablesHighest SKU Processors - Summary Description Revision HistoryRev # Rev. DateProjects Covered RevisionProject Document State Page 1Applications 1.1Introduction and TerminologyTable 1-2.Guideline Categories 2Output Voltage Requirements 2.1Voltage and Current - REQUIREDSustained Current A Time Duration sOutput Voltage Requirements 2.2Load Line Definitions - REQUIREDTable 2-2.Icc Guidelines Table 2-3.VID Select, LL1, LL0 Codes Sheet 1 of 2.3Voltage Tolerance - REQUIRED Table 2-3.VID Select, LL1, LL0 Codes Sheet 2 of2.4Processor VCC Overshoot - REQUIRED 2.5Impedance vs. Frequency - EXPECTED500 kHz Ztarget = Z LLVR BW 700 kHz2.7Processor Power Sequencing - REQUIRED 2.6Stability - REQUIRED5V/12V VBOOT=1.1VPWM Vcc VTT VTT PWRGD OUTEN VID SELECT Tg2.8Dynamic Voltage Identification D-VID REQUIRED Figure 2-5.Processor Transition States 2.9Overshoot at Turn-Onor Turn-Off- REQUIRED 2.10Output Filter Capacitance - REQUIREDFigure Figure Figure 6 layers, 2 power, 2 ground, 2 signal, 1 oz Cu Motherboard Socket & Package2.11Shut-DownResponse - REQUIRED 3.2Voltage Identification VID 6 0 - REQUIRED 3Control Signals3.1Output Enable OUTEN - REQUIRED Control Signals 315889-0023.3Differential Remote Sense VO SEN+ REQUIRED Socket Table 3-6.VID Bit Mapping 3.4Load Line Select LL0, LL1, VID Select REQUIREDTable 3-5.LL0, LL1, VID Select Specifications Control Signals 4.2Load Transient Effects on Input Current 4Input Voltage and Current4.1Input Voltages - EXPECTED EXPECTEDInput Voltage and Current 5.2Over-CurrentProtection OCP - EXPECTED 5Processor Voltage Output Protection5.1Over-VoltageProtection OVP - EXPECTED Processor Voltage Output Protection 6.2Voltage Regulator Hot VR hot# - PROPOSED 6Output Indicators6.1Voltage Regulator Ready VR Ready - REQUIRED 6.5VR Identification VR ID# - EXPECTED 6.3Load Indicator Output Load Current PROPOSED6.4VRM Present VRM pres# - EXPECTED Table 6-3.VRM pres# SpecificationsOutput Indicators VRM Pres#Output Indicators 7.2.1Connector Keying 7.1VRM Connector - EXPECTED7.2VRM Tyco/Elcon Connector Keying 7.2.2Connector Pin 1 OrientationName Table 7-2.VRM 11.0 Connector Pin DescriptionsVRM - Mechanical Guidelines Type7.4Mechanical Dimensions - PROPOSED 7.4.1Gold Finger SpecificationFigure 7-1.VRM 11.0 Module and Connector PCB Footprint8.3Non-OperatingTemperature - PROPOSED 8.1Operating Temperature - PROPOSED8.2VRM Board Temperature - REQUIRED 8Environmental Conditions8.6Electrostatic Discharge - PROPOSED 8.10Safety - PROPOSED8.5Altitude - PROPOSED 8.7Shock and Vibration - PROPOSED9Manufacturing Considerations 9.1Lead Free Pb FreeManufacturing Considerations A.1 Introduction - PROPOSED AZf Constant Output Impedance DesignFigure A-2.Zf Network Plot with 1.25 mΩ Load Line Page A.2 Voltage Transient Tool VTT Zf Theory Z f = FFT V t FFT I tA.3 VTT Zf Measurement Method A.4 ResultsPage 10uF 22uF A.5 Output Decoupling Design Procedure