VRM and Enterprise Voltage Regulator-DownEVRD
Voltage Regulator Module
Design Guidelines
April
315889-002
Applications
Contents
Tables
Figures
Highest SKU Processors - Summary
Rev #
Revision History
Description
Rev. Date
Project Document State
Revision
Projects Covered
Page
1.1Introduction and Terminology
1Applications
Table 1-2.Guideline Categories
2.1Voltage and Current - REQUIRED
2Output Voltage Requirements
Time Duration s
Sustained Current A
Table 2-2.Icc Guidelines
2.2Load Line Definitions - REQUIRED
Output Voltage Requirements
Table 2-3.VID Select, LL1, LL0 Codes Sheet 1 of
Table 2-3.VID Select, LL1, LL0 Codes Sheet 2 of
2.3Voltage Tolerance - REQUIRED
2.5Impedance vs. Frequency - EXPECTED
2.4Processor VCC Overshoot - REQUIRED
VR BW
Ztarget = Z LL
500 kHz
700 kHz
2.6Stability - REQUIRED
2.7Processor Power Sequencing - REQUIRED
PWM Vcc
VBOOT=1.1V
5V/12V
VTT VTT PWRGD OUTEN VID SELECT Tg
2.8Dynamic Voltage Identification D-VID REQUIRED
Figure 2-5.Processor Transition States
2.10Output Filter Capacitance - REQUIRED
2.9Overshoot at Turn-Onor Turn-Off- REQUIRED
Figure Figure Figure
6 layers, 2 power, 2 ground, 2 signal, 1 oz Cu
Socket & Package
Motherboard
2.11Shut-DownResponse - REQUIRED
3.1Output Enable OUTEN - REQUIRED
3Control Signals
3.2Voltage Identification VID 6 0 - REQUIRED
315889-002
Control Signals
3.3Differential Remote Sense VO SEN+ REQUIRED
Socket
Table 3-5.LL0, LL1, VID Select Specifications
3.4Load Line Select LL0, LL1, VID Select REQUIRED
Table 3-6.VID Bit Mapping
Control Signals
4.1Input Voltages - EXPECTED
4Input Voltage and Current
4.2Load Transient Effects on Input Current
EXPECTED
Input Voltage and Current
5.1Over-VoltageProtection OVP - EXPECTED
5Processor Voltage Output Protection
5.2Over-CurrentProtection OCP - EXPECTED
Processor Voltage Output Protection
6.1Voltage Regulator Ready VR Ready - REQUIRED
6Output Indicators
6.2Voltage Regulator Hot VR hot# - PROPOSED
6.4VRM Present VRM pres# - EXPECTED
6.3Load Indicator Output Load Current PROPOSED
6.5VR Identification VR ID# - EXPECTED
Table 6-3.VRM pres# Specifications
VRM Pres#
Output Indicators
Output Indicators
7.2VRM Tyco/Elcon Connector Keying
7.1VRM Connector - EXPECTED
7.2.1Connector Keying
7.2.2Connector Pin 1 Orientation
VRM - Mechanical Guidelines
Table 7-2.VRM 11.0 Connector Pin Descriptions
Name
Type
7.4.1Gold Finger Specification
7.4Mechanical Dimensions - PROPOSED
PCB Footprint
Figure 7-1.VRM 11.0 Module and Connector
8.2VRM Board Temperature - REQUIRED
8.1Operating Temperature - PROPOSED
8.3Non-OperatingTemperature - PROPOSED
8Environmental Conditions
8.5Altitude - PROPOSED
8.10Safety - PROPOSED
8.6Electrostatic Discharge - PROPOSED
8.7Shock and Vibration - PROPOSED
9.1Lead Free Pb Free
9Manufacturing Considerations
Manufacturing Considerations
AZf Constant Output Impedance Design
A.1 Introduction - PROPOSED
Figure A-2.Zf Network Plot with 1.25 mΩ Load Line
Page
Z f = FFT V t FFT I t
A.2 Voltage Transient Tool VTT Zf Theory
A.4 Results
A.3 VTT Zf Measurement Method
Page
10uF 22uF
A.5 Output Decoupling Design Procedure
