Intel 315889-002 manual A.5 Output Decoupling Design Procedure

Z(f) Constant Output Impedance Design

Figure A-8. Simulated and Measured Waveforms of Platform Impedance Profile

measured vs simulated results

	10
		meas:allcaps
	9	meas:bank1-9+2oscons
		sim:swvr-allcaps
	8	sim:avgvr-allcaps
		sim:swvr-bank1-9+2osc
	7	sim:avgvr-bank1-9+2osc
(mohms)	6
	5
impedance
	4
	3
	2
	1
	0
	10-3	10-2	10-1	100	101
			frequency(MHz)

A.5 Output Decoupling Design Procedure

1.Select type and number of bulk capacitors. Normally the equivalent ESR needs to be approximately ½ the load line target impedance. For a 1.25 mΩ load line, the equivalent ESR should be less than 0.625 mΩ. The reason for selecting the number of bulk capacitors to yield an equivalent ESR to be ½ the target impedance is to compensate for the parasitic resistance of the PCB layout plane shapes and for aging of the capacitors. This is a starting point for the design. The final number of bulk capacitors will be determined by transient droop testing and Z(f) measurements.

2.The type and number of MLCC capacitors in the socket cavity is specified in the Section 2.10. These are required to meet both power delivery impedance and signal integrity issues.

3.Design the PWM loop bandwidth compensation. The ideal loop BW is set at the frequency where the bulk capacitor impedance meets the target impedance curve. In Figure A-2, it is approximately 30 kHz. Small increases in the loop bandwidth will not improve system performance until the bandwidth is moved to where the MLCC impedance meets the target impedance at ~ 700 kHz which is impractical.

Consult the PWM chip manufacturer's data sheets and application notes on calculating the PWM loop compensation and AVP programming values.

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