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Intel 315889-002 manual Revision, Project Document State, Projects Covered

Models: 315889-002

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The following table lists the revision schedule based on revision number and development stage of the product.

Revision	Project Document State	Projects Covered

0.5	Preliminary Targets	HW, SW

0.5 to 0.9	Updates to Most Recent Update or 0.5	HW, SW

1.0	Design Frozen	HW, SW

1.0 to 1.5	Updates to Most Recent Update or 1.0	HW, SW

1.5	Preliminary Validation Data (Doc-Dependent)	HW Only

1.6 to 1.75	Updates to Most Recent Update or 1.5	HW Only

1.75	(Optional) Final Validation Data (Doc-Dependent)	HW Only

1.76 to 1.9	Updates to Most Recent Update or 1.75	HW Only

Launch	Launch Documents	HW Only

Note: Not all revisions may be published.

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Intel 315889-002 manual Revision, Project Document State, Projects Covered

Contents

April Voltage Regulator ModuleVRM and Enterprise Voltage Regulator-DownEVRD Design Guidelines315889-002 Applications ContentsTables FiguresHighest SKU Processors - Summary Rev. Date Revision HistoryRev # DescriptionProject Document State RevisionProjects Covered Page 1.1Introduction and Terminology 1ApplicationsTable 1-2.Guideline Categories 2.1Voltage and Current - REQUIRED 2Output Voltage RequirementsTime Duration s Sustained Current ATable 2-2.Icc Guidelines 2.2Load Line Definitions - REQUIREDOutput Voltage Requirements Table 2-3.VID Select, LL1, LL0 Codes Sheet 1 of Table 2-3.VID Select, LL1, LL0 Codes Sheet 2 of 2.3Voltage Tolerance - REQUIRED2.5Impedance vs. Frequency - EXPECTED 2.4Processor VCC Overshoot - REQUIRED700 kHz Ztarget = Z LLVR BW 500 kHz2.6Stability - REQUIRED 2.7Processor Power Sequencing - REQUIREDVTT VTT PWRGD OUTEN VID SELECT Tg VBOOT=1.1VPWM Vcc 5V/12V2.8Dynamic Voltage Identification D-VID REQUIRED Figure 2-5.Processor Transition States 2.10Output Filter Capacitance - REQUIRED 2.9Overshoot at Turn-Onor Turn-Off- REQUIREDFigure Figure Figure 6 layers, 2 power, 2 ground, 2 signal, 1 oz Cu Socket & Package Motherboard2.11Shut-DownResponse - REQUIRED 3.1Output Enable OUTEN - REQUIRED 3Control Signals3.2Voltage Identification VID 6 0 - REQUIRED 315889-002 Control Signals3.3Differential Remote Sense VO SEN+ REQUIRED Socket Table 3-5.LL0, LL1, VID Select Specifications 3.4Load Line Select LL0, LL1, VID Select REQUIREDTable 3-6.VID Bit Mapping Control Signals EXPECTED 4Input Voltage and Current4.1Input Voltages - EXPECTED 4.2Load Transient Effects on Input CurrentInput Voltage and Current 5.1Over-VoltageProtection OVP - EXPECTED 5Processor Voltage Output Protection5.2Over-CurrentProtection OCP - EXPECTED Processor Voltage Output Protection 6.1Voltage Regulator Ready VR Ready - REQUIRED 6Output Indicators6.2Voltage Regulator Hot VR hot# - PROPOSED Table 6-3.VRM pres# Specifications 6.3Load Indicator Output Load Current PROPOSED6.4VRM Present VRM pres# - EXPECTED 6.5VR Identification VR ID# - EXPECTEDVRM Pres# Output IndicatorsOutput Indicators 7.2.2Connector Pin 1 Orientation 7.1VRM Connector - EXPECTED7.2VRM Tyco/Elcon Connector Keying 7.2.1Connector KeyingType Table 7-2.VRM 11.0 Connector Pin DescriptionsVRM - Mechanical Guidelines Name7.4.1Gold Finger Specification 7.4Mechanical Dimensions - PROPOSEDPCB Footprint Figure 7-1.VRM 11.0 Module and Connector8Environmental Conditions 8.1Operating Temperature - PROPOSED8.2VRM Board Temperature - REQUIRED 8.3Non-OperatingTemperature - PROPOSED8.7Shock and Vibration - PROPOSED 8.10Safety - PROPOSED8.5Altitude - PROPOSED 8.6Electrostatic Discharge - PROPOSED9.1Lead Free Pb Free 9Manufacturing ConsiderationsManufacturing Considerations AZf Constant Output Impedance Design A.1 Introduction - PROPOSEDFigure A-2.Zf Network Plot with 1.25 mΩ Load Line Page Z f = FFT V t FFT I t A.2 Voltage Transient Tool VTT Zf TheoryA.4 Results A.3 VTT Zf Measurement MethodPage 10uF 22uF A.5 Output Decoupling Design Procedure