Intel 315889-002 Dynamic Voltage Identification D-VID, Startup Sequence Timing Parameters Sheet 2

					Output Voltage Requirements
Table 2-5. Startup Sequence Timing Parameters (Sheet 2 of 2)
	Timing	Min	Default	Max	Remarks
	Td =	0	0.25 ms	2.5 ms	Programmable soft start ramp;
	VccCPU rise time to final VID				Measured from 10-90% of slope
	Te =	0.05 ms		3.0 ms
	VccCPU to VR_READY
	assertion time
	Tf =	0.05 ms		10.0 ms	Measured from 10-90% of slope
	Vtt rise time
	Tg =	0		5.0 ms
	OUTEN to Vcc_CPU rising -
	delay time

Note:

1.Minimum delays must be selected in a manner which will guarantee compliance to voltage tolerance specifications.

2.8Dynamic Voltage Identification (D-VID) -

REQUIRED

VRM/EVRD 11.0 supports dynamic VID across the entire VID table. The VRM/EVRD must be capable of accepting voltage level changes of 12.5 mV steps every 5 µs. The low voltage state will be maintained for at least 50 µs. The worst case settling time, including line-to-line skew, for the seven VID lines is 400 ns. The VID inputs should contain circuitry to prevent false tripping or latching of VID codes during the settling time.

During a transition, the output voltage must be between the maximum voltage of the high range (“A” in Figure 2-5) and the minimum voltage of the low range (“B”). The VRM/EVRD must respond to a transition from VID-low to VID-high by regulating its Vcc output to the range defined by the new final VID code, within 50 µs of the final step. The time to move the output voltage from VID-high to VID-low will depend on the PWM controller design, the amount of system decoupling capacitance, and the processor load.

Figure 2-5shows operating states as a representative processor changes levels. The diagram assumes steady state, maximum current during the transition for ease of illustration; actual processor behavior allows for any dIcc/dt event during the transitions, depending on the code it is executing at that time. In the example, the processor begins in a high-load condition. In transitions 1-2 and 2-3, the processor prepares to switch to the low-voltage range with a transition to a low load condition, followed by an increased activity level. Transition 3-4 is a simplification of the multiple steps from the high-voltage load line to the low-voltage load line. Transition 4-5 is an example of a response to a load change during normal operation in the lower range.

20 315889-002