Manuals / Intel / Household Appliance / Thermostat

Intel 315889-002 manual Revision History, Rev #, Description, Rev. Date

Models: 315889-002

1 56

Download 56 pages 18.09 Kb

Page 6

Revision History

Revision History

	Rev #		Description	Rev. Date

	001	•	Initial Release	November 2006

	002	• General- Update Harpertown and Wolfdale-DP to public names		April 2008
	002	•	Table 2-3 correction - Loadline ID codes for 5400/5200 series processors	April 2008
		•

6	315889-002

Image 6

Intel 315889-002 manual Revision History, Rev #, Description, Rev. Date

Contents

Design Guidelines Voltage Regulator ModuleVRM and Enterprise Voltage Regulator-DownEVRD April315889-002 Contents ApplicationsFigures TablesHighest SKU Processors - Summary Description Revision HistoryRev # Rev. DateRevision Project Document StateProjects Covered Page 1Applications 1.1Introduction and TerminologyTable 1-2.Guideline Categories 2Output Voltage Requirements 2.1Voltage and Current - REQUIREDSustained Current A Time Duration s2.2Load Line Definitions - REQUIRED Table 2-2.Icc GuidelinesOutput Voltage Requirements Table 2-3.VID Select, LL1, LL0 Codes Sheet 1 of 2.3Voltage Tolerance - REQUIRED Table 2-3.VID Select, LL1, LL0 Codes Sheet 2 of2.4Processor VCC Overshoot - REQUIRED 2.5Impedance vs. Frequency - EXPECTED500 kHz Ztarget = Z LLVR BW 700 kHz2.7Processor Power Sequencing - REQUIRED 2.6Stability - REQUIRED5V/12V VBOOT=1.1VPWM Vcc VTT VTT PWRGD OUTEN VID SELECT Tg2.8Dynamic Voltage Identification D-VID REQUIRED Figure 2-5.Processor Transition States 2.9Overshoot at Turn-Onor Turn-Off- REQUIRED 2.10Output Filter Capacitance - REQUIREDFigure Figure Figure 6 layers, 2 power, 2 ground, 2 signal, 1 oz Cu Motherboard Socket & Package2.11Shut-DownResponse - REQUIRED 3Control Signals 3.1Output Enable OUTEN - REQUIRED3.2Voltage Identification VID 6 0 - REQUIRED Control Signals 315889-0023.3Differential Remote Sense VO SEN+ REQUIRED Socket 3.4Load Line Select LL0, LL1, VID Select REQUIRED Table 3-5.LL0, LL1, VID Select SpecificationsTable 3-6.VID Bit Mapping Control Signals 4.2Load Transient Effects on Input Current 4Input Voltage and Current4.1Input Voltages - EXPECTED EXPECTEDInput Voltage and Current 5Processor Voltage Output Protection 5.1Over-VoltageProtection OVP - EXPECTED5.2Over-CurrentProtection OCP - EXPECTED Processor Voltage Output Protection 6Output Indicators 6.1Voltage Regulator Ready VR Ready - REQUIRED6.2Voltage Regulator Hot VR hot# - PROPOSED 6.5VR Identification VR ID# - EXPECTED 6.3Load Indicator Output Load Current PROPOSED6.4VRM Present VRM pres# - EXPECTED Table 6-3.VRM pres# SpecificationsOutput Indicators VRM Pres#Output Indicators 7.2.1Connector Keying 7.1VRM Connector - EXPECTED7.2VRM Tyco/Elcon Connector Keying 7.2.2Connector Pin 1 OrientationName Table 7-2.VRM 11.0 Connector Pin DescriptionsVRM - Mechanical Guidelines Type7.4Mechanical Dimensions - PROPOSED 7.4.1Gold Finger SpecificationFigure 7-1.VRM 11.0 Module and Connector PCB Footprint8.3Non-OperatingTemperature - PROPOSED 8.1Operating Temperature - PROPOSED8.2VRM Board Temperature - REQUIRED 8Environmental Conditions8.6Electrostatic Discharge - PROPOSED 8.10Safety - PROPOSED8.5Altitude - PROPOSED 8.7Shock and Vibration - PROPOSED9Manufacturing Considerations 9.1Lead Free Pb FreeManufacturing Considerations A.1 Introduction - PROPOSED AZf Constant Output Impedance DesignFigure A-2.Zf Network Plot with 1.25 mΩ Load Line Page A.2 Voltage Transient Tool VTT Zf Theory Z f = FFT V t FFT I tA.3 VTT Zf Measurement Method A.4 ResultsPage 10uF 22uF A.5 Output Decoupling Design Procedure