Intel 315889-002 manual 5.Processor Transition States

Output Voltage Requirements

Figure 2-5. Processor Transition States

VID High Load Line 2

A

3

Icc-max

VID Low Load Line

5

1

B

4

Figure 2-6is an example of dynamic VID. The diagram assumes steady state, constant current during the dynamic VID transition for ease of illustration; actual processor behavior allows for any dIcc/dt during the transitions, depending on the code it is executing at that time. Note that during dynamic VID, the processor will not output VID codes that would disable the voltage regulator output voltage.

Figure 2-6. Dynamic VID Transition States Illustration

ext.

VR11		VR10
						36 VID steps @ 5 s each step = 180us
	table	table
VID 1		VID 5			400ns
			worst case VID
VID 2		VID 0		settling time
VID 3		VID 1
VID 4		VID 2
VID 5		VID 3
VID 6		VID 4

Note: VR11 table – VID 0 and extended VR10 table – VID 6 is reserved for future processors

450mV

low VID to high VID
Vcc
	transition		Maximum
					Vcc
high VID to low VID
				settling
Vcc	transition
		450mV

					Upper equals
				Final VID - 1.25 m			* Icc
					Lower equals
	50µs maximum	settling		Start VID - 1.25		m * Icc - 30mV
	from registering final VID
50µs maximum settling
					Upper equals
from registering final VID
				Final VID - 1.25 m			* Icc
					Lower equals
			Start VID - 1.25 m * Icc - 30mV

The diagram assumes steady state, constant current during the dynamic VID transitions for ease of illustration; actual processor behavior allows for any dIcc/dt event during the transitions, depending on the code it is executing at that time

The processor load may not be sufficient to absorb all of the energy from the output capacitors on the baseboard, when VIDs change to a lower output voltage. The VRM/ EVRD design should ensure that any energy transfer from the capacitors does not impair the operation of the VRM/EVRD, the AC-DC supply, or any other parts of the system.

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