Intel 315889-002 manual 2.3Voltage Tolerance - REQUIRED, 3.VID Select, LL1, LL0 Codes Sheet 2 of

Output Voltage Requirements

Table 2-3. VID_Select, LL1, LL0 Codes (Sheet 2 of 2)

VID	VID_	LL1	LL0		Load Line / Processors
Table	Select
	0	0	0	VccMAX =	VID (V) –1.25 mΩ • Icc (A)	V	3
				VccMIN =	VID (V) –1.25 mΩ • Icc (A) –30 mV
mode
	0	0	1	VccMAX =	VID (V) –1.25 mΩ • Icc (A)	V	2, 3
				VccMIN =	VID (V) –1.25 mΩ • Icc (A) –30 mV
VR10.2
	0	1	0	VccMAX =	VID (V) –1.25 mΩ • Icc (A)	V	1, 3
				VccMIN =	VID (V) –1.25 mΩ • Icc (A) –30 mV
	0	1	1	VccMAX =	reserved	V	3, 4
				VccMIN =	reserved
	1	0	0	VccMAX =	VID (V) –1.00 mΩ • Icc (A)	V	1, 3
				VccMIN =	VID (V) –1.00 mΩ • Icc (A) –30 mV
mode
	1	0	1	VccMAX =	VID (V) –1.25 mΩ • Icc (A)	V	1, 3
				VccMIN =	VID (V) –1.25 mΩ • Icc (A) –30 mV
VR11.0
	1	1	0	VccMAX =	VID (V) –1.50 mΩ • Icc (A)	V	1, 3
				VccMIN =	VID (V) –1.50 mΩ • Icc (A) –30 mV
	1	1	1	VccMAX =	VID (V) –1.25 mΩ • Icc (A)	V	1, 3
				VccMIN =	VID (V) –1.25 mΩ • Icc (A) –30 mV

Notes:

1.The Vcc values are the expected voltage measured at the processor die.

2.The Dual-Core Intel® Xeon® 7100 series / Dual-Core Intel® Xeon® processor 7000 sequence entry is required for backward compatibility for VR ‘modules’ only using the EVRD/VRM 10.2, but the VRM11.0 should be backward compatible with VRM10.2 platforms, as modular VRs can be transferred from one platform to another.

3.For VRM 11.0 mode, VRM_Pres# and VR_ID# should be held LOW for all combinations as described in Section 6.

2.3Voltage Tolerance - REQUIRED

The voltage ranges shown in Section 2.2 include the following tolerances:

•Initial DC output voltage set-point error.

•Output ripple and noise.

•No-load offset centering error.

•Current sensing and droop errors.

•Component aging affect.

•Full ambient temperature range and warm up.

•Dynamic output changes from minimum-to-maximum and maximum-to-minimum load should be measured at the point of regulation. When measuring the response of the die voltage to dynamic loads, use the VCC_DIE_SENSE and VSS_DIE_SENSE or VCC_DIE_SENSE2 and VSS_DIE_SENSE2 pins on the processor socket with an oscilloscope set to a DC to 20-100 MHz bandwidth limit and with probes that are 1.5 pF maximum and 1 MW minimum impedance.

•Variations of the input voltage.

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