Intel 315889-002 manual 3.VID Select, LL1, LL0 Codes Sheet 1 of

Output Voltage Requirements

The upper and lower load lines represent the allowable range of voltages that must be presented to the processor. The voltage must always stay within these boundaries for proper operation of the processor. Operating above the VCCMAX load line limit will result in higher processor operating temperature, which may result in damage or a reduced processor lifespan. Processor temperature rise from higher functional voltages may lead to dynamic operation to low power states, which directly reduces processor performance. Operating below the VCCMIN load line limit will result in minimum voltage violations, which will result in reduced processor performance, system lock up, “blue screens” or data corruption.

For load line validation information, please refer to the LGA771-V2 Voltage Test Tool User’s Guide.

Figure 2-2and Figure 2-2shows the load line voltage offsets and current levels based on the VID specifications for the core regulator.

The encoding in Table 2-2for the load lines is valid for the range of load current from 0 A to 150 A. The VID_Select, load line 1 (LL1), and load line 0 (LL0) control signals from Section 3.4, form a 3-bit load line selection and will be used to configure the VRM/ EVRD to supply the proper load lines for the platforms in Table 1-1. Refer to Figure 6-1for additional encoding requirements for VRMs. For implementation of VID_Select, LL0, and LL1 on the baseboard refer to the appropriate platform design guidelines. The VID_Select control signal will select the appropriate VR10 or VR11 table and remap the external VID [6:0] pins to the appropriate DAC input. This line will be pulled up externally to the VTT rail (1.1 V/1.2 V ± 5%) via a recommended 4.7 kΩ resistor on the baseboard and will be programmed by the processor package. The processor does not support 5 V or 12 V levels and these should not be used. The VID_Select signal should be logic low or tied to ground for extended VR10 table selection. A logic high will indicate a VR11 table selection. The VID_Select will not toggle during normal operation.

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Table 2-3. VID_Select, LL1, LL0 Codes (Sheet 1 of 2)

VID	VID_	LL1	LL0	Load Line / Processors
Table	Select
	0	0	0	1.25 mΩ; Reserved
VR10.2	0	0	1	1.25 mΩ; Dual-Core Intel® Xeon® Processor 5000 Series / MV
	0	1	0	processor LGA771 die Load Line
				1.25 mΩ; Dual-Core Intel® Xeon® processor 7000 series / Dual-Core
				Intel® Xeon® 7100 series processor mPGA604 die Load Line
	0	1	1	Reserved
	1	0	0	1.00 mΩ; Reserved
				1.25 mΩ; Dual-Core Intel® Xeon® Processor 5100 Series, Dual-Core
VR11.0	1	0	1	Intel® Xeon® Processor 5200 Series, Quad-Core Intel® Xeon®
				Processor 5400 Series, Dual-Core Intel® Xeon® Processor 7200
				Series, Quad-Core Intel® Xeon® Processor 7300 Series
	1	1	0	1.50 mΩ; Reserved
	1	1	1	1.25 mΩ; Quad-Core Intel Xeon processor 5300 Series
VID	VID_	LL1	LL0	VCC Tolerance / Die Load Line	Units	Notes
Table	Select

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