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Intel 315889-002 manual A.1 Introduction - PROPOSED, AZf Constant Output Impedance Design

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AZ(f) Constant Output Impedance Design

Z(f) Constant Output Impedance Design

AZ(f) Constant Output Impedance Design

A.1 Introduction - PROPOSED

The VRM/EVRD performance specification is based on the concept of output impedance, commonly known as the load line. The impedance is determined by the Pulse Width Modulator (PWM) controller’s Adaptive Voltage Positioning (AVP), up to the loop bandwidth of the regulator and the impedance of the output filter and socket beyond the loop bandwidth.

Figure A-1. Typical Intel® Microprocessor Voltage Regulator Validation Setup

	ZPCB1	ZPCB2	ZPskt
Vin			VTT
ZBulk	ZHF1	ZHF2	VTT
PWM
	VFB

315889-002

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Intel 315889-002 manual A.1 Introduction - PROPOSED, AZf Constant Output Impedance Design

Contents

VRM and Enterprise Voltage Regulator-DownEVRD Voltage Regulator ModuleDesign Guidelines April315889-002 Applications ContentsTables FiguresHighest SKU Processors - Summary Rev # Revision HistoryDescription Rev. DateProject Document State RevisionProjects Covered Page 1.1Introduction and Terminology 1ApplicationsTable 1-2.Guideline Categories 2.1Voltage and Current - REQUIRED 2Output Voltage RequirementsTime Duration s Sustained Current ATable 2-2.Icc Guidelines 2.2Load Line Definitions - REQUIREDOutput Voltage Requirements Table 2-3.VID Select, LL1, LL0 Codes Sheet 1 of Table 2-3.VID Select, LL1, LL0 Codes Sheet 2 of 2.3Voltage Tolerance - REQUIRED2.5Impedance vs. Frequency - EXPECTED 2.4Processor VCC Overshoot - REQUIREDVR BW Ztarget = Z LL500 kHz 700 kHz2.6Stability - REQUIRED 2.7Processor Power Sequencing - REQUIREDPWM Vcc VBOOT=1.1V5V/12V VTT VTT PWRGD OUTEN VID SELECT Tg2.8Dynamic Voltage Identification D-VID REQUIRED Figure 2-5.Processor Transition States 2.10Output Filter Capacitance - REQUIRED 2.9Overshoot at Turn-Onor Turn-Off- REQUIREDFigure Figure Figure 6 layers, 2 power, 2 ground, 2 signal, 1 oz Cu Socket & Package Motherboard2.11Shut-DownResponse - REQUIRED 3.1Output Enable OUTEN - REQUIRED 3Control Signals3.2Voltage Identification VID 6 0 - REQUIRED 315889-002 Control Signals3.3Differential Remote Sense VO SEN+ REQUIRED Socket Table 3-5.LL0, LL1, VID Select Specifications 3.4Load Line Select LL0, LL1, VID Select REQUIREDTable 3-6.VID Bit Mapping Control Signals 4.1Input Voltages - EXPECTED 4Input Voltage and Current4.2Load Transient Effects on Input Current EXPECTEDInput Voltage and Current 5.1Over-VoltageProtection OVP - EXPECTED 5Processor Voltage Output Protection5.2Over-CurrentProtection OCP - EXPECTED Processor Voltage Output Protection 6.1Voltage Regulator Ready VR Ready - REQUIRED 6Output Indicators6.2Voltage Regulator Hot VR hot# - PROPOSED 6.4VRM Present VRM pres# - EXPECTED 6.3Load Indicator Output Load Current PROPOSED6.5VR Identification VR ID# - EXPECTED Table 6-3.VRM pres# SpecificationsVRM Pres# Output IndicatorsOutput Indicators 7.2VRM Tyco/Elcon Connector Keying 7.1VRM Connector - EXPECTED7.2.1Connector Keying 7.2.2Connector Pin 1 OrientationVRM - Mechanical Guidelines Table 7-2.VRM 11.0 Connector Pin DescriptionsName Type7.4.1Gold Finger Specification 7.4Mechanical Dimensions - PROPOSEDPCB Footprint Figure 7-1.VRM 11.0 Module and Connector8.2VRM Board Temperature - REQUIRED 8.1Operating Temperature - PROPOSED8.3Non-OperatingTemperature - PROPOSED 8Environmental Conditions8.5Altitude - PROPOSED 8.10Safety - PROPOSED8.6Electrostatic Discharge - PROPOSED 8.7Shock and Vibration - PROPOSED9.1Lead Free Pb Free 9Manufacturing ConsiderationsManufacturing Considerations AZf Constant Output Impedance Design A.1 Introduction - PROPOSEDFigure A-2.Zf Network Plot with 1.25 mΩ Load Line Page Z f = FFT V t FFT I t A.2 Voltage Transient Tool VTT Zf TheoryA.4 Results A.3 VTT Zf Measurement MethodPage 10uF 22uF A.5 Output Decoupling Design Procedure