Intel 315889-002 PWM Vcc, 5V/12V, VTT VTT PWRGD OUTEN VID SELECT Tg, Vcc CPU, Vr Ready, VID bits

Output Voltage Requirements

Figure 2-4. Power-On Sequence Timing Diagram

BCLK [1:0] (for reference only)

PWM Vcc

(5V/12V)

Tf Ta

VTT

VTT_PWRGD

OUTEN

VID_SELECT Tg

(pulled up to VTT)	Tc
	VBOOT=1.1V
Vcc_CPU	Td	Te
	Tb

VR_READY

VID bits

/ BSEL[2:0]

CPU_PWGOOD (from platform, for reference only)

RESET# (for reference only)

VCCPLL

(for reference only)

VID code read by PWM at the end of Tc VID valid

Notes:

1.VTT_PWRGD can be designed to be driving directly the OUTEN input.

2.Tb and Td voltage slopes are determined by soft start logic of the PWM controller.

3.Vboot is a default power-on Vcc (Core) value. Upon detection of a valid Vtt supply, the PWM controller is to regulate to this value until the VID codes are read. The Vboot voltage is 1.1 V

4.VTT is the processor termination regulator’s output voltage and the VTT_PWRGD is the VTT regulator’s power good status indicator.

5.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

6.This specification requires that the VID signals be sampled no earlier than 10 µs after VCC (at VCC_BOOT voltage) and VTT are stable.

7.Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply is in regulation as defined by the minimum and maximum DC/AC specifications for all components being powered by it.

8.The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor. Measured between (0.3 * VTT) and (0.7 * VTT).

Table 2-5. Startup Sequence Timing Parameters (Sheet 1 of 2)

Timing	Min	Default	Max	Remarks
Ta =				If the actual timing exceeds 2ms, the
PWM Vcc & Vtt to OUTEN delay	0	2.0 ms	5.0 ms	VTT VR must be capable of
				supporting full Itt surge current
time
				requirement per Proc’s latest EMTS
Tb =	0.05 ms1	0.5 ms	10.0 ms	Programmable soft start ramp;
Vboot rise time				Measured from 10-90% of slope
Tc =	0.05 ms1		3.0 ms
Vboot to VID valid delay time

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