Intel 315889-002 manual 3.4Load Line Select LL0, LL1, VID Select REQUIRED, 6.VID Bit Mapping

Control Signals

3.4Load Line Select (LL0, LL1, VID_Select) -

REQUIRED

The VID_Select, LL1 and LL0 control signal form a 3-bit load line selection and will used to configure the VRM/EVRD to supply the proper load line for the processors. These signals are programmed by the CPU package pin bonding. The VID_Select control signal will select the appropriate VR10 or VR11 VID table and remap the VID [6:0] pins to the appropriate DAC input. The signals are open-collector/drain or equivalent signals. Table 3-5shows the VID_Select, LL1, and LL0 pins specification and Table 3-6

shows equations in how to obtain VMAX and VMIN based on LL0, LL1, and VID_Select bit code. For VRMs a set of additional signals extent the usability of a modular solution,

refer to Figure 6-1.

It is EXPECTED that the pull-up resistors for LL0 and LL1 will be located on the baseboard and will not be integrated into the VRM. However, the pull-up resistor for VID_Select should be located on the VRM and to maintain backward compatibility to VRM 10.2 compliant platforms a pull-down resistor of 10 kΩ is also required. The pull- down resistor is required for VRMs only and not required for EVRDs. Typically, for EVRD converters, this signal will be pulled up to VTT (1.1 V/1.2 V) via a 4.7 kΩ resistor. As an option, 3.3 V with ± 5% regulation tolerance, may be used instead of VTT for VRM or EVRD converters. Pull-ups to 12 V or 5 V are not supported by the CPU package.

The VR 10 and VR 11.0 VID pins do not have the same voltage weight. See Table 3-6for the VID bit mapping.

Table 3-5. LL0, LL1, VID_Select Specifications

Symbol	Parameter	Min	Max	Units
IOL	Output Low Current	0	4	mA
VIH	Input Voltage High	0.8	3.465	V
VIL	Input Voltage Low	0	0.4	V

Table 3-6. VID Bit Mapping

VR 10.x	-	VID 4	VID 3	VID 2	VID 1	VID 0	VID 5	VID 6
bit	800mV	400mV	200mV	100mV	50mV	25mV	12.5mV	6.25mV
weight
VR 11.0	VID 7	VID 6	VID 5	VID 4	VID 3	VID 2	VID 1	VID 0

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