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manual Design Guide, Intel 41210 Serial to Parallel PCI Bridge
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41210
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Specs
41210 Bridge Microcontroller Block Diagram
Dimension
SMBus for configuration register initialization
Bridge Reset and Power Timing Considerations5
PCI-X Signals
Checklist
Power Plane Layout
PCB Ground Layout Around Connectors
PCI Express Interface Features
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Intel® 41210 Serial to Parallel PCI Bridge
Design Guide
May 2005
Order Number:
278801-004
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Contents
Intel 41210 Serial to Parallel PCI Bridge
Design Guide
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Contents
Contents
Introduction
Contents
Figures
Revision History
Tables
Contents
SMBUs Address Configuration
Contents
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Intel 41210 Serial to Parallel PCI Bridge Design Guide
1.1 Terminology and Definitions
About This Document
Table 1. Terminology and Definitions Sheet 1 of
Table 1. Terminology and Definitions Sheet 2 of
About This Document
Intel 41210 Serial to Parallel PCI Bridge Design Guide
2.2 PCI-X Interface Features
2.1 PCI Express Interface Features
Introduction2
2.4.1 SMBus for configuration register initialization
2.3 Power Management
2.4 SMBus Interface
Introduction
2.4.2 Microcontroller Connections to the 41210 Bridge
Figure 1. 41210 Bridge Microcontroller Block Diagram
Figure 2. 41210 Bridge Microcontroller Connections
Configuration
2.5 JTAG
Figure 3. 41210 Bridge Block Diagram
2.6 Related Documents
Intelfi 41210 Bridge A
2.7 Intel41210 Serial to Parallel PCI Bridge Applications
Figure 4. Intel 41210 Bridge Adapter Card Block Diagram
Introduction
Introduction
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Intel 41210 Serial to Parallel PCI Bridge Design Guide
Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions
3.1 Package Specification
Package Information
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Package Information
B2711-01
Package Information
Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions
Intel 41210 Serial to Parallel PCI Bridge Design Guide
B2712-01
Package Information
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Intel 41210 Serial to Parallel PCI Bridge Design Guide
4.1 41210 Bridge Decoupling Guidelines
Power Plane Layout
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Power Plane Layout
Capacitor Legend
B2714-01
Table 2. 41210 Bridge Decoupling Guidelines
4.2 Split Voltage Planes
Power Plane Layout
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Power Plane Layout
Figure 10. 41210 Bridge Single-Layer Split Voltage Plane
PCI Express
Core
5.1 ARST#,BRST# and PERST# Timing Requirements
41210 Bridge Reset and Power Timing Considerations5
5.2 VCC15 and VCC33 Voltage Requirements
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41210 Bridge Reset and Power Timing Considerations
Intel 41210 Serial to Parallel PCI Bridge Design Guide
6.1 General Routing Guidelines
General Routing Guidelines
6.2 Crosstalk
6.3 EMI Considerations
Figure 12. PCB Ground Layout Around Connectors
General Routing Guidelines
Figure 11. Crosstalk Effects on Trace Distance and Height
6.5 Trace Impedance
6.4 Power Distribution and Decoupling
6.4.1 Decoupling
http//emclab.umr.edu/pcbtlc
Figure 13. Cross Section of Differential Trace
6.5.1 Differential Impedance
Figure 14. Two-by-two Differential Impedance Matrix
Z11 Z12 Z21 Z22
7.1 Adapter Card Topology
Board Layout Guidelines
Adapter Card Stack Up, Microstrip and Stripline
Figure 15. Adapter Card Stackup
Board Layout Guidelines
Intel 41210 Serial to Parallel PCI Bridge Design Guide
8.1 Interrupts
PCI-X Layout Guidelines
Table 4. INTx Routing Table
8.1.1 Interrupt Routing for Devices Behind a Bridge
8.2 PCI Arbitration
PCI-X Layout Guidelines
Table 5. Interrupt Binding for Devices Behind a Bridge
8.2.1 PCI Resistor Compensation
8.3 PCI General Layout Guidelines
Figure 16. PCI RCOMP
PCI-X Layout Guidelines
8.3.1 PCI Pullup Resistors Not Required
Table 6. PCI-X Signals
Table 7. PCI/PCI-X Frequency/Mode Straps
PCI-X Layout Guidelines
PCI-X Layout Guidelines
8.4 PCI Clock Layout Guidelines
PCI-X Layout Guidelines
Figure 17. PCI Clock Distribution and Matching Requirements
Intel 41210 Bridge
PCI Device PCI Device PCI Device PCI Device PCI Device
PCI-X Layout Guidelines
PCI-X Clock Layout Requirements Summary
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Parameter
PCI-X Slot Guidelines
8.5 PCI-X Topology Layout Guidelines
PCI-X Layout Guidelines
Figure 18. Embedded PCI-X 133 MHz Topology
8.6.1 Embedded PCI-X 133 MHz
Embedded PCI-X 133 MHz Routing Recommendations
PCI-X Layout Guidelines
Figure 19. Embedded PCI-X 100 MHz Topology
8.6.2 Embedded PCI-X 100 MHz
Embedded PCI-X 100 MHz Routing Recommendations
PCI-X Layout Guidelines
Figure 20. PCI-X 66 MHz Embedded Routing Topology
8.6.3 PCI-X 66 MHz Embedded Topology
PCI-X 66 MHz Embedded Routing Recommendations
PCI-X Layout Guidelines
Figure 21. PCI 66 MHz Embedded Topology
8.6.4 PCI 66 MHz Embedded Topology
PCI 66 MHz Embedded Table
PCI-X Layout Guidelines
Figure 22. PCI 33 MHz Embedded Mode Routing Topology
8.6.5 PCI 33 MHz Embedded Mode Topology
PCI 33 MHz Embedded Routing Recommendations
PCI-X Layout Guidelines
PCI-X Layout Guidelines
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Intel 41210 Serial to Parallel PCI Bridge Design Guide
9.1 General recommendations
PCI Express Layout
9.3 Adapter Card Layout Guidelines
9.2 PCI-Express Layout Guidelines
PCI Express Layout
Adapter Card Routing Recommendations Sheet 1 of
PCI Express Layout
Table 15. Adapter Card Routing Recommendations Sheet 2 of
Intel 41210 Serial to Parallel PCI Bridge Design Guide
PCI Express Layout
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Intel 41210 Serial to Parallel PCI Bridge Design Guide
10.1 41210 Bridge Analog Voltage Filters
Circuit Implementations
10.1.2 PCI Express Analog Voltage Filter
10.1.1 PCI Analog Voltage Filters
Circuit Implementations
Figure 23. PCI Analog Voltage Filter Circuit
Figure 24. PCI Express Analog Voltage Filter Circuit
10.1.3 Bandgap Analog Voltage Filter
Circuit Implementations
Circuit Implementations
Bandgap Analog Voltage Filter Circuit
B2726
Circuit Implementations
Figure 26. Reference and Compensation Circuit Implementations
10.2.1 SM Bus
Table 17. SMBUs Address Configuration
Circuit Implementations
Boards
41210 Bridge Customer Reference
11.1 Board Stack-up
Intel 41210 Serial to Parallel PCI Bridge Design Guide
11.3 Impedance
11.2 Material
41210 Bridge Customer Reference Boards
Table 18. CRB Board Stackup
Figure 27. Mechanical Outline of the 41210 Bridge
11.4 Board Outline
41210 Bridge Customer Reference Boards
U1 Intelfi Bridge
41210 Bridge Customer Reference Boards
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Intel 41210 Serial to Parallel PCI Bridge Design Guide
Table 19. PCI Express Interface Signals
Design Guide Checklist
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Table 20. PCI/PCI-X Interface Signals
Design Guide Checklist
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Table 20. PCI/PCI-X Interface Signals
Design Guide Checklist
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Design without secondary PCI/PCI
Table 22. SMBus Interface Signals
Table 21. Miscellaneous Signals
Design Guide Checklist
To retry configuration accesses to the 41210, pull high to
Design Guide Checklist
Table 23. Power and Ground Signals
power down or any other time during system operation
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Design Guide Checklist
Table 24. JTAG Signals
Intel 41210 Serial to Parallel PCI Bridge Design Guide
