Intel 41210 manual Jtag, Related Documents

Introduction

2.5JTAG

•Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a

2.6Related Documents

•Intel® 41210 Serial to Parallel PCI Bridge Design Specification (EDS), Revision 1.0.

•PCI Express Specification, Revision 1.0, from www.pci-sig.com.

•PCI Express Design Guide, Revision 0.5

•PCI Local Bus Specification, Revision 2.3, from www.pci-sig.com.

•PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, from www.pci-sig.com.

•IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a

•System Management Bus Specification, Revision 2.0

Figure 3. 41210 Bridge Block Diagram

PCI-Express x8

JTAG SMB Bus

Intelfi

41210 Bridge A

Bus Arbiter

A

Clock Buffer

B

Bus Arbiter

B

Clock Buffer

A_PCLKI B_PCLKI

A Bus PCI-X 133MHz

6 REQ/GNT Pairs

6 A_PCLKO

B Bus PCI-X 133MHz

6 REQ/GNT Pairs

6 B_PCLKO

B2709-01

12 Intel® 41210 Serial to Parallel PCI Bridge Design Guide