8.6.4PCI 66 MHz Embedded Topology
Figure 21 and Table 13 provide routing details for a topology with an embedded PCI 66 MHz design.
Figure 21. PCI 66 MHz Embedded Topology
| EM1 | EM3 | ||||
| TL EM1 |
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| TL EM3 |
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| TL1 |
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| TL2 |
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| TL EM2 |
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| TL EM4 |
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| EM2 | EM4 | ||||
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| B2722 | |
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Table 13. | PCI 66 MHz Embedded Table |
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| Routing Guideline for Lower AD Bus |
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| Reference Plane |
| Route over an unbroken ground plane |
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| Board Impedance |
| 60 Ω | +/- 15% |
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| Microstrip Trace Spacing |
| 18 mils center to center |
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| Stripline Trace Spacing |
| 12 mils center to center |
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| Group Spacing |
| Spacing from other groups: 25 mils min, edge to edge |
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| Breakout |
| 5 mils on 5 mils spacing. Maximum length of breakout |
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| region can be 500 mils. |
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| Trace Length 1 TL1: From 41210 Bridge signal Ball |
| 5.0” max |
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| to first junction |
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| Trace Length TL2 between junctions |
| 0.5” min - 3.5” max |
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| Trace Length TL_EM1 to TL_EM4 from junction to |
| 2.0” min - 3.0” max |
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| embedded devices |
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| Length Matching Requirements |
| Clocks coming from the clock driver must be length |
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| matched to within 25 mils. |
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| Number of vias |
| 4 vias max. |
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P
42 | Intel® 41210 Serial to Parallel PCI Bridge Design Guide |
