PCI-X Layout Guidelines, Interrupts | Intel 41210 instruction

PCI-X Layout Guidelines

8

This chapter describes several factors to be considered with a 41210 Bridge PCI/PCI-X design. These include the PCI IDSEL, PCI RCOMP, PCI Interrupts and PCI arbitration.

8.1Interrupts

PCI Express provides interrupt messages that emulate the legacy wired mechanism. This allows IO devices to signal PCI-style interrupts using a pair of ASSERT and DEASSERT messages This message pairing preserves the level-sensitive semantics of the PCI interrupts on PCI Express.

The 41210 Bridge uses four interrupts - A_INTA:A_INTD on bus A segment and four interrupts B_INTA:B_INTD that corresponding to the four interrupts defined in the PCI specification. The 41210 Bridge routes its PCI interrupt pins and the internal interrupts, to PCI Express INTx interrupts according to Table 4.

Table 4. INTx Routing Table

A_INT# Interrupt Pins	B_INT# Interrupt Pins	PCI Express INTx Message

A_INTA	B_INTA	INTA

A_INTB	B_INTB	INTB

A_INTC	B_INTC	INTC

A_INTD	B_INTD	INTD

The 41210 Bridge will use its primary bus number and device number in the Requester ID field for the PCI Express INTx messages. As stated in the PCI Express specification, the function number is reserved for interrupt messages and will always be 0.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 manual PCI-X Layout Guidelines, Interrupts, INTx Routing Table

Contents

Design Guide Intel 41210 Serial to Parallel PCI Bridge Intel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Revision History TablesDescription This page intentionally left blank Term Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1 Terminology and Definitions Sheet 2 About This Document PCI-X Interface Features PCI Express Interface FeaturesIntroduction2 Introduction Power ManagementSMBus for configuration register initialization SMBus Interface Microcontroller Connections to the 41210 Bridge Bridge Microcontroller Block Diagram Related Documents Jtag Intel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Bridge Adapter Card Block Diagram This page intentionally left blank Package Information Package Specification Package Information Bottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Side View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank 41210 Bridge Decoupling Guidelines Power Plane Layout Power Plane Layout Bridge Decoupling Guidelines Split Voltage Planes PCI ARST#,BRST# and PERST# Timing Requirements Bridge Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI Considerations Trace Impedance Power Distribution and DecouplingDecoupling Cross Section of Differential Trace Differential Impedance Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout Guidelines Interrupts PCI-X Layout GuidelinesINTx Routing Table Interrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout Guidelines PCI Resistor Compensation PCI General Layout Guidelines PCI Pullup Resistors Not Required PCI-X SignalsPCI/PCI-X Frequency/Mode Straps BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Layout Guidelines PCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary PCI-X Slot Guidelines PCI-X Topology Layout Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHz PCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 66 MHz Embedded Topology PCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode Topology This page intentionally left blank General recommendations PCI Express Layout Adapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express Layout Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41210 Bridge Analog Voltage Filters PCI Express Analog Voltage Filter PCI Analog Voltage FiltersCircuit Implementations Vccape Bandgap Analog Voltage FilterVssape Vccbgpe Bandgap Analog Voltage Filter CircuitVSS Vssbgpe PERCOMP0 PERCOMP1 Rcomp Reference and Compensation Circuit Implementations SM Bus SMBUs Address ConfigurationBit Value Board Stack-up Bridge Customer Reference Boards Bridge Customer Reference Boards Layer Type Thickness Copper WeightMaterial Impedance Mechanical Outline of the 41210 Bridge Board Outline This page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/Impact PCI/PCI-X Interface Signals Design Guide Checklist Bpcixcap AM66ENBM66EN PERST# Apcixcap SMBus Interface Signals Miscellaneous SignalsSignals VCC33 Power and Ground SignalsSignal Recommendations Reason/Impact VCC15 Jtag Signals