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Intel manual Intel41210 Serial to Parallel PCI Bridge Applications, Introduction

Models: 41210

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Introduction

2.7Intel®41210 Serial to Parallel PCI Bridge Applications

This section provides a block diagram for a typical the 41210 Bridge application. This application shows a PCI-E adapter card with two Dual 2Gb Fibre Channel controllers. Each of the PCI-X bus segments is connected to the Dual 2Gb Fibre Channel chip running at 133MHz. The two Dual FC chips provides the four 2Gb/s outputs.

Figure 4. Intel® 41210 Bridge Adapter Card Block Diagram

I2C Micro Controller

Intel® 41210

Bridge

PCI-X to

PCI Express

Dual 2Gb

133MHz

PCI-X

Dual 2Gb

SFP Optical		2 Gb/s
Module		2 Gb/s
Module
SFP Optical		2 Gb/s
Module		2 Gb/s
Module
SFP Optical		2 Gb/s
Module		2 Gb/s
Module
SFP Optical		2 Gb/s
Module		2 Gb/s
Module

	PCI Express	This is locally configurable from SMBus or
		PCI-X interfaces (no BIOS support or Drivers
	(to Server)
		required)

B1491-02

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

Page 13

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Intel manual Intel41210 Serial to Parallel PCI Bridge Applications, Intel 41210 Bridge Adapter Card Block Diagram

Contents

Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents ContentsIntroduction Contents FiguresRevision History TablesContents SMBUs Address ConfigurationContents This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 1.1 Terminology and Definitions About This DocumentTable 1. Terminology and Definitions Sheet 1 of Table 1. Terminology and Definitions Sheet 2 of About This DocumentIntel 41210 Serial to Parallel PCI Bridge Design Guide 2.2 PCI-X Interface Features 2.1 PCI Express Interface FeaturesIntroduction2 2.4.1 SMBus for configuration register initialization 2.3 Power Management2.4 SMBus Interface Introduction2.4.2 Microcontroller Connections to the 41210 Bridge Figure 1. 41210 Bridge Microcontroller Block DiagramFigure 2. 41210 Bridge Microcontroller Connections Configuration2.5 JTAG Figure 3. 41210 Bridge Block Diagram2.6 Related Documents Intelﬁ 41210 Bridge A2.7 Intel41210 Serial to Parallel PCI Bridge Applications Figure 4. Intel 41210 Bridge Adapter Card Block DiagramIntroduction Introduction This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions 3.1 Package SpecificationPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Package InformationB2711-01 Package Information Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package DimensionsIntel 41210 Serial to Parallel PCI Bridge Design Guide B2712-01Package Information This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 4.1 41210 Bridge Decoupling Guidelines Power Plane LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Power Plane LayoutCapacitor Legend B2714-01Table 2. 41210 Bridge Decoupling Guidelines 4.2 Split Voltage PlanesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuidePower Plane Layout Figure 10. 41210 Bridge Single-Layer Split Voltage PlanePCI Express Core5.1 ARST#,BRST# and PERST# Timing Requirements 41210 Bridge Reset and Power Timing Considerations55.2 VCC15 and VCC33 Voltage Requirements This page intentionally left blank 41210 Bridge Reset and Power Timing ConsiderationsIntel 41210 Serial to Parallel PCI Bridge Design Guide 6.1 General Routing Guidelines General Routing Guidelines6.2 Crosstalk 6.3 EMI Considerations Figure 12. PCB Ground Layout Around ConnectorsGeneral Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height6.5 Trace Impedance 6.4 Power Distribution and Decoupling6.4.1 Decoupling http//emclab.umr.edu/pcbtlcFigure 13. Cross Section of Differential Trace 6.5.1 Differential ImpedanceFigure 14. Two-by-two Differential Impedance Matrix Z11 Z12 Z21 Z227.1 Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Figure 15. Adapter Card Stackup Board Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide 8.1 Interrupts PCI-X Layout GuidelinesTable 4. INTx Routing Table 8.1.1 Interrupt Routing for Devices Behind a Bridge 8.2 PCI ArbitrationPCI-X Layout Guidelines Table 5. Interrupt Binding for Devices Behind a Bridge8.2.1 PCI Resistor Compensation 8.3 PCI General Layout GuidelinesFigure 16. PCI RCOMP PCI-X Layout Guidelines8.3.1 PCI Pullup Resistors Not Required Table 6. PCI-X SignalsTable 7. PCI/PCI-X Frequency/Mode Straps PCI-X Layout GuidelinesPCI-X Layout Guidelines 8.4 PCI Clock Layout GuidelinesPCI-X Layout Guidelines Figure 17. PCI Clock Distribution and Matching RequirementsIntel 41210 Bridge PCI Device PCI Device PCI Device PCI Device PCI DevicePCI-X Layout Guidelines PCI-X Clock Layout Requirements SummaryIntel 41210 Serial to Parallel PCI Bridge Design Guide ParameterPCI-X Slot Guidelines 8.5 PCI-X Topology Layout GuidelinesPCI-X Layout Guidelines Figure 18. Embedded PCI-X 133 MHz Topology 8.6.1 Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations PCI-X Layout GuidelinesFigure 19. Embedded PCI-X 100 MHz Topology 8.6.2 Embedded PCI-X 100 MHzEmbedded PCI-X 100 MHz Routing Recommendations PCI-X Layout GuidelinesFigure 20. PCI-X 66 MHz Embedded Routing Topology 8.6.3 PCI-X 66 MHz Embedded TopologyPCI-X 66 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesFigure 21. PCI 66 MHz Embedded Topology 8.6.4 PCI 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI-X Layout GuidelinesFigure 22. PCI 33 MHz Embedded Mode Routing Topology 8.6.5 PCI 33 MHz Embedded Mode TopologyPCI 33 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesPCI-X Layout Guidelines This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 9.1 General recommendations PCI Express Layout9.3 Adapter Card Layout Guidelines 9.2 PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 ofPCI Express Layout Table 15. Adapter Card Routing Recommendations Sheet 2 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI Express Layout This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 10.1 41210 Bridge Analog Voltage Filters Circuit Implementations10.1.2 PCI Express Analog Voltage Filter 10.1.1 PCI Analog Voltage FiltersCircuit Implementations Figure 23. PCI Analog Voltage Filter CircuitFigure 24. PCI Express Analog Voltage Filter Circuit 10.1.3 Bandgap Analog Voltage FilterCircuit Implementations Circuit Implementations Bandgap Analog Voltage Filter CircuitB2726 Circuit Implementations Figure 26. Reference and Compensation Circuit Implementations10.2.1 SM Bus Table 17. SMBUs Address ConfigurationCircuit Implementations Boards 41210 Bridge Customer Reference11.1 Board Stack-up Intel 41210 Serial to Parallel PCI Bridge Design Guide11.3 Impedance 11.2 Material41210 Bridge Customer Reference Boards Table 18. CRB Board StackupFigure 27. Mechanical Outline of the 41210 Bridge 11.4 Board Outline41210 Bridge Customer Reference Boards U1 Intelﬁ Bridge41210 Bridge Customer Reference Boards This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 19. PCI Express Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 20. PCI/PCI-X Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 20. PCI/PCI-X Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCITable 22. SMBus Interface Signals Table 21. Miscellaneous SignalsDesign Guide Checklist To retry configuration accesses to the 41210, pull high toDesign Guide Checklist Table 23. Power and Ground Signalspower down or any other time during system operation Intel 41210 Serial to Parallel PCI Bridge Design GuideDesign Guide Checklist Table 24. JTAG SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide