Intel 41210 manual Tables, Revision History, Contents, PCI-X Clock Layout Requirements Summary

					Contents
22	PCI 33 MHz Embedded Mode Routing Topology				43
23	PCI Analog Voltage Filter Circuit				50
24	PCI Express Analog Voltage Filter Circuit				51
25	Bandgap Analog Voltage Filter Circuit				52
26	Reference and Compensation Circuit Implementations				53
27	Proposed Mechanical Outline of the 41210 Bridge				57
Tables
1	Terminology and Definitions				7
2	41210 Bridge Decoupling Guidelines				21
3	Adapter Card Stack Up, Microstrip and Stripline				29
4	INTx Routing Table				31
5	Interrupt Binding for Devices Behind a Bridge				32
6	PCI-X Signals				34
7	PCI/PCI-X Frequency/Mode Straps				34
8	PCI-X Clock Layout Requirements Summary			.............................................................................	37
9	PCI-X Slot Guidelines				38
10	Embedded PCI-X 133 MHz Routing Recommendations				39
11	Embedded PCI-X 100 MHz Routing Recommendations				40
12	PCI-X 66 MHz Embedded Routing Recommendations				41
13	PCI 66 MHz Embedded Table				42
14	PCI 33 MHz Embedded Routing Recommendations				43
15	Adapter Card Routing Recommendations				46
16	Recommended R, L and C Values for 41210 Bridge Analog Filter Circuits				49
17	SMBUs Address Configuration		...................................................................................................		54
18	CRB Board Stackup				56
19	PCI Express Interface Signals				59
20	PCI/PCI-X Interface Signals				60
21	Miscellaneous Signals				62
22	SMBus Interface Signals				62
23	Power and Ground Signals				63
24	JTAG Signals				64
Revision History
		Date	Revision	Description
				Removed Section 5.3, VCCPE and REFCLKn/REFCLKp
		May 2005	004	Information
				Added signals to Section 8.3.1
				Updated Table 19, Table 20, and Table 21
				Updated PCI Express operation information in Section 2.1 and
		October 2004	003	Table 19.
				Added signal NC17 information in Table 21.
		July 2004	002	Updated Chapters 4, 5, and 12
		October 2003	001	Updated content; second draft of this document; initial public
				release of this document.
		July 2003	000	First internal draft of this document.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide v