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Intel manual Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions, Package Information

Models: 41210

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Package Information

Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions

FC BGA Substrate

Die

1.940 – 0.150

		Detail	J
H		Scale	5:1
H
			0.74 – 0.025
			0.100 – 0.025
			Die Solder
			Bumps
		Underfill
Detail	H	Epoxy
Scale	5:1
		1.170 – 0.085
		0.600 – 0.100

BGA Solder Balls

B2712-01

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Image 17

Intel manual Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions, Package Information, B2712-01

Contents

Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Introduction ContentsContents Contents FiguresRevision History TablesContents SMBUs Address ConfigurationIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankContents Table 1. Terminology and Definitions Sheet 1 of About This Document1.1 Terminology and Definitions Intel 41210 Serial to Parallel PCI Bridge Design Guide About This DocumentTable 1. Terminology and Definitions Sheet 2 of Introduction2 2.1 PCI Express Interface Features2.2 PCI-X Interface Features 2.4.1 SMBus for configuration register initialization 2.3 Power Management2.4 SMBus Interface Introduction2.4.2 Microcontroller Connections to the 41210 Bridge Figure 1. 41210 Bridge Microcontroller Block DiagramFigure 2. 41210 Bridge Microcontroller Connections Configuration2.5 JTAG Figure 3. 41210 Bridge Block Diagram2.6 Related Documents Intelﬁ 41210 Bridge AIntroduction Figure 4. Intel 41210 Bridge Adapter Card Block Diagram2.7 Intel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankIntroduction Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions 3.1 Package SpecificationPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideB2711-01 Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide Package Information Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package DimensionsIntel 41210 Serial to Parallel PCI Bridge Design Guide B2712-01Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPackage Information 4.1 41210 Bridge Decoupling Guidelines Power Plane LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Power Plane LayoutCapacitor Legend B2714-01Table 2. 41210 Bridge Decoupling Guidelines 4.2 Split Voltage PlanesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuidePower Plane Layout Figure 10. 41210 Bridge Single-Layer Split Voltage PlanePCI Express Core5.2 VCC15 and VCC33 Voltage Requirements 41210 Bridge Reset and Power Timing Considerations55.1 ARST#,BRST# and PERST# Timing Requirements Intel 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Reset and Power Timing ConsiderationsThis page intentionally left blank 6.2 Crosstalk General Routing Guidelines6.1 General Routing Guidelines 6.3 EMI Considerations Figure 12. PCB Ground Layout Around ConnectorsGeneral Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height6.5 Trace Impedance 6.4 Power Distribution and Decoupling6.4.1 Decoupling http//emclab.umr.edu/pcbtlcFigure 13. Cross Section of Differential Trace 6.5.1 Differential ImpedanceFigure 14. Two-by-two Differential Impedance Matrix Z11 Z12 Z21 Z22Adapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines7.1 Adapter Card Topology Intel 41210 Serial to Parallel PCI Bridge Design Guide Board Layout GuidelinesFigure 15. Adapter Card Stackup Table 4. INTx Routing Table PCI-X Layout Guidelines8.1 Interrupts 8.1.1 Interrupt Routing for Devices Behind a Bridge 8.2 PCI ArbitrationPCI-X Layout Guidelines Table 5. Interrupt Binding for Devices Behind a Bridge8.2.1 PCI Resistor Compensation 8.3 PCI General Layout GuidelinesFigure 16. PCI RCOMP PCI-X Layout Guidelines8.3.1 PCI Pullup Resistors Not Required Table 6. PCI-X SignalsTable 7. PCI/PCI-X Frequency/Mode Straps PCI-X Layout GuidelinesPCI-X Layout Guidelines 8.4 PCI Clock Layout GuidelinesPCI-X Layout Guidelines Figure 17. PCI Clock Distribution and Matching RequirementsIntel 41210 Bridge PCI Device PCI Device PCI Device PCI Device PCI DevicePCI-X Layout Guidelines PCI-X Clock Layout Requirements SummaryIntel 41210 Serial to Parallel PCI Bridge Design Guide ParameterPCI-X Layout Guidelines 8.5 PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Figure 18. Embedded PCI-X 133 MHz Topology 8.6.1 Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations PCI-X Layout GuidelinesFigure 19. Embedded PCI-X 100 MHz Topology 8.6.2 Embedded PCI-X 100 MHzEmbedded PCI-X 100 MHz Routing Recommendations PCI-X Layout GuidelinesFigure 20. PCI-X 66 MHz Embedded Routing Topology 8.6.3 PCI-X 66 MHz Embedded TopologyPCI-X 66 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesFigure 21. PCI 66 MHz Embedded Topology 8.6.4 PCI 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI-X Layout GuidelinesFigure 22. PCI 33 MHz Embedded Mode Routing Topology 8.6.5 PCI 33 MHz Embedded Mode TopologyPCI 33 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPCI-X Layout Guidelines 9.1 General recommendations PCI Express Layout9.3 Adapter Card Layout Guidelines 9.2 PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 15. Adapter Card Routing Recommendations Sheet 2 ofPCI Express Layout Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPCI Express Layout 10.1 41210 Bridge Analog Voltage Filters Circuit Implementations10.1.2 PCI Express Analog Voltage Filter 10.1.1 PCI Analog Voltage FiltersCircuit Implementations Figure 23. PCI Analog Voltage Filter CircuitCircuit Implementations 10.1.3 Bandgap Analog Voltage FilterFigure 24. PCI Express Analog Voltage Filter Circuit B2726 Bandgap Analog Voltage Filter CircuitCircuit Implementations Circuit Implementations Figure 26. Reference and Compensation Circuit ImplementationsCircuit Implementations Table 17. SMBUs Address Configuration10.2.1 SM Bus Boards 41210 Bridge Customer Reference11.1 Board Stack-up Intel 41210 Serial to Parallel PCI Bridge Design Guide11.3 Impedance 11.2 Material41210 Bridge Customer Reference Boards Table 18. CRB Board StackupFigure 27. Mechanical Outline of the 41210 Bridge 11.4 Board Outline41210 Bridge Customer Reference Boards U1 Intelﬁ BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blank41210 Bridge Customer Reference Boards Intel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide ChecklistTable 19. PCI Express Interface Signals Intel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide ChecklistTable 20. PCI/PCI-X Interface Signals Table 20. PCI/PCI-X Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCITable 22. SMBus Interface Signals Table 21. Miscellaneous SignalsDesign Guide Checklist To retry configuration accesses to the 41210, pull high toDesign Guide Checklist Table 23. Power and Ground Signalspower down or any other time during system operation Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 24. JTAG SignalsDesign Guide Checklist