Power Management, SMBus Interface, Introduction | Intel 41210

Introduction

•Tunable inbound read prefetch algorithm for PCI MRM/MRL commands

•Local initialization via SMBus

•Secondary side initialization via Type 0 configuration cycles.

2.3Power Management

•Support for PCI Express Active State Power Management (ASPM) L0s link state

•Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states

•Support for PME# event propagation on behalf of PCI devices

2.4SMBus Interface

•Compatible with System Management Bus Specification, Revision 2.0

•Slave mode operation only.

•Full read/write access to all configuration registers

2.4.1SMBus for configuration register initialization

•Support for local initialization of the configuration registers can be implemented using a microcontroller via SMB. Figure 1shows this SMBus and the data transfer that occurs between the 41210 Bridge and the microcontroller.

•Configuration Register information is stored internally in a microcontroller and the information is transferred to the product via System Managed Bus (SMBus) protocols when the device receives power or reset.

•The requirements of the microcontroller are as follows:

—Supports I2C and SMBus Protocols

—Has at least 256 Byte of internal EEprom space

—To facilitate this programming on the Customer Reference Board a Microchip part PIC16F876A was used.

—Code space: estimated code size is ~2K words of program space and 32 words of RAM

10	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

Image 10

Intel 41210 manual Power Management, SMBus Interface, SMBus for configuration register initialization, Introduction

Contents

Intel 41210 Serial to Parallel PCI Bridge Design Guide Intel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Revision History TablesDescription This page intentionally left blank Terminology and Definitions Sheet 1 About This DocumentTerminology and Definitions Term Definition About This Document Terminology and Definitions Sheet 2 PCI-X Interface Features PCI Express Interface FeaturesIntroduction2 SMBus Interface Power ManagementSMBus for configuration register initialization Introduction Bridge Microcontroller Block Diagram Microcontroller Connections to the 41210 Bridge Jtag Related Documents Intel 41210 Bridge Adapter Card Block Diagram Intel41210 Serial to Parallel PCI Bridge Applications This page intentionally left blank Package Specification Package Information Bottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Package Information Side View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank Power Plane Layout 41210 Bridge Decoupling Guidelines Power Plane Layout Split Voltage Planes Bridge Decoupling Guidelines PCI ARST#,BRST# and PERST# Timing Requirements Bridge Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing Guidelines Trace Impedance Power Distribution and DecouplingDecoupling Differential Impedance Cross Section of Differential Trace Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card Stackup Interrupts PCI-X Layout GuidelinesINTx Routing Table PCI-X Layout Guidelines PCI ArbitrationInterrupt Routing for Devices Behind a Bridge Interrupt Binding for Devices Behind a Bridge PCI General Layout Guidelines PCI Resistor Compensation PCI Pullup Resistors Not Required PCI-X SignalsPCI/PCI-X Frequency/Mode Straps PCI Clock Layout Guidelines BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines PCI-X Topology Layout Guidelines PCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing Recommendations PCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing Recommendations PCI 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing Recommendations This page intentionally left blank PCI Express Layout General recommendations PCI Express Layout PCI-Express Layout GuidelinesAdapter Card Layout Guidelines Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41210 Bridge Analog Voltage Filters PCI Express Analog Voltage Filter PCI Analog Voltage FiltersCircuit Implementations Vccape Bandgap Analog Voltage FilterVssape Vccbgpe Bandgap Analog Voltage Filter CircuitVSS Vssbgpe Reference and Compensation Circuit Implementations PERCOMP0 PERCOMP1 Rcomp SM Bus SMBUs Address ConfigurationBit Value Bridge Customer Reference Boards Board Stack-up Impedance Layer Type Thickness Copper WeightMaterial Bridge Customer Reference Boards Board Outline Mechanical Outline of the 41210 Bridge This page intentionally left blank Signals Recommendations Reason/Impact Design Guide ChecklistPCI Express Interface Signals PERCOMP10 Design Guide Checklist PCI/PCI-X Interface Signals Apcixcap AM66ENBM66EN PERST# Bpcixcap SMBus Interface Signals Miscellaneous SignalsSignals VCC15 Power and Ground SignalsSignal Recommendations Reason/Impact VCC33 Jtag Signals