Introduction
•Tunable inbound read prefetch algorithm for PCI MRM/MRL commands
•Local initialization via SMBus
•Secondary side initialization via Type 0 configuration cycles.
2.3Power Management
•Support for PCI Express Active State Power Management (ASPM) L0s link state
•Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states
•Support for PME# event propagation on behalf of PCI devices
2.4SMBus Interface
•Compatible with System Management Bus Specification, Revision 2.0
•Slave mode operation only.
•Full read/write access to all configuration registers
2.4.1SMBus for configuration register initialization
•Support for local initialization of the configuration registers can be implemented using a microcontroller via SMB. Figure 1shows this SMBus and the data transfer that occurs between the 41210 Bridge and the microcontroller.
•Configuration Register information is stored internally in a microcontroller and the information is transferred to the product via System Managed Bus (SMBus) protocols when the device receives power or reset.
•The requirements of the microcontroller are as follows:
—Supports I2C and SMBus Protocols
—Has at least 256 Byte of internal EEprom space
—To facilitate this programming on the Customer Reference Board a Microchip part PIC16F876A was used.
—Code space: estimated code size is ~2K words of program space and 32 words of RAM
10 | Intel® 41210 Serial to Parallel PCI Bridge Design Guide |
