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Specification
41210 Bridge Microcontroller Block Diagram
Dimension
SMBus for configuration register initialization
Bridge Reset and Power Timing Considerations5
PCI-X Signals
Checklist
Power Plane Layout
PCB Ground Layout Around Connectors
PCI Express Interface Features
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Contents
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Intel® 41210 Serial to Parallel PCI Bridge Design Guide
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Contents
Design Guide
Intel 41210 Serial to Parallel PCI Bridge
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Contents
Contents
Introduction
Figures
Contents
Contents
Tables
Revision History
SMBUs Address Configuration
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Contents
Intel 41210 Serial to Parallel PCI Bridge Design Guide
About This Document
1.1 Terminology and Definitions
Table 1. Terminology and Definitions Sheet 1 of
About This Document
Table 1. Terminology and Definitions Sheet 2 of
Intel 41210 Serial to Parallel PCI Bridge Design Guide
2.1 PCI Express Interface Features
2.2 PCI-X Interface Features
Introduction2
2.4 SMBus Interface
2.3 Power Management
2.4.1 SMBus for configuration register initialization
Introduction
Figure 2. 41210 Bridge Microcontroller Connections
Figure 1. 41210 Bridge Microcontroller Block Diagram
2.4.2 Microcontroller Connections to the 41210 Bridge
Configuration
2.6 Related Documents
Figure 3. 41210 Bridge Block Diagram
2.5 JTAG
Intelfi 41210 Bridge A
Figure 4. Intel 41210 Bridge Adapter Card Block Diagram
2.7 Intel41210 Serial to Parallel PCI Bridge Applications
Introduction
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Introduction
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Package Information
3.1 Package Specification
Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Package Information
Intel 41210 Serial to Parallel PCI Bridge Design Guide
B2711-01
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions
Package Information
B2712-01
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Package Information
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Power Plane Layout
4.1 41210 Bridge Decoupling Guidelines
Capacitor Legend
Power Plane Layout
Intel 41210 Serial to Parallel PCI Bridge Design Guide
B2714-01
Power Plane Layout
4.2 Split Voltage Planes
Table 2. 41210 Bridge Decoupling Guidelines
Intel 41210 Serial to Parallel PCI Bridge Design Guide
PCI Express
Figure 10. 41210 Bridge Single-Layer Split Voltage Plane
Power Plane Layout
Core
41210 Bridge Reset and Power Timing Considerations5
5.1 ARST#,BRST# and PERST# Timing Requirements
5.2 VCC15 and VCC33 Voltage Requirements
41210 Bridge Reset and Power Timing Considerations
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Intel 41210 Serial to Parallel PCI Bridge Design Guide
General Routing Guidelines
6.1 General Routing Guidelines
6.2 Crosstalk
General Routing Guidelines
Figure 12. PCB Ground Layout Around Connectors
6.3 EMI Considerations
Figure 11. Crosstalk Effects on Trace Distance and Height
6.4.1 Decoupling
6.4 Power Distribution and Decoupling
6.5 Trace Impedance
http//emclab.umr.edu/pcbtlc
Figure 14. Two-by-two Differential Impedance Matrix
6.5.1 Differential Impedance
Figure 13. Cross Section of Differential Trace
Z11 Z12 Z21 Z22
Board Layout Guidelines
7.1 Adapter Card Topology
Adapter Card Stack Up, Microstrip and Stripline
Board Layout Guidelines
Figure 15. Adapter Card Stackup
Intel 41210 Serial to Parallel PCI Bridge Design Guide
PCI-X Layout Guidelines
8.1 Interrupts
Table 4. INTx Routing Table
PCI-X Layout Guidelines
8.2 PCI Arbitration
8.1.1 Interrupt Routing for Devices Behind a Bridge
Table 5. Interrupt Binding for Devices Behind a Bridge
Figure 16. PCI RCOMP
8.3 PCI General Layout Guidelines
8.2.1 PCI Resistor Compensation
PCI-X Layout Guidelines
Table 7. PCI/PCI-X Frequency/Mode Straps
Table 6. PCI-X Signals
8.3.1 PCI Pullup Resistors Not Required
PCI-X Layout Guidelines
8.4 PCI Clock Layout Guidelines
PCI-X Layout Guidelines
Intel 41210 Bridge
Figure 17. PCI Clock Distribution and Matching Requirements
PCI-X Layout Guidelines
PCI Device PCI Device PCI Device PCI Device PCI Device
Intel 41210 Serial to Parallel PCI Bridge Design Guide
PCI-X Clock Layout Requirements Summary
PCI-X Layout Guidelines
Parameter
8.5 PCI-X Topology Layout Guidelines
PCI-X Slot Guidelines
PCI-X Layout Guidelines
Embedded PCI-X 133 MHz Routing Recommendations
8.6.1 Embedded PCI-X 133 MHz
Figure 18. Embedded PCI-X 133 MHz Topology
PCI-X Layout Guidelines
Embedded PCI-X 100 MHz Routing Recommendations
8.6.2 Embedded PCI-X 100 MHz
Figure 19. Embedded PCI-X 100 MHz Topology
PCI-X Layout Guidelines
PCI-X 66 MHz Embedded Routing Recommendations
8.6.3 PCI-X 66 MHz Embedded Topology
Figure 20. PCI-X 66 MHz Embedded Routing Topology
PCI-X Layout Guidelines
PCI 66 MHz Embedded Table
8.6.4 PCI 66 MHz Embedded Topology
Figure 21. PCI 66 MHz Embedded Topology
PCI-X Layout Guidelines
PCI 33 MHz Embedded Routing Recommendations
8.6.5 PCI 33 MHz Embedded Mode Topology
Figure 22. PCI 33 MHz Embedded Mode Routing Topology
PCI-X Layout Guidelines
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PCI-X Layout Guidelines
Intel 41210 Serial to Parallel PCI Bridge Design Guide
PCI Express Layout
9.1 General recommendations
PCI Express Layout
9.2 PCI-Express Layout Guidelines
9.3 Adapter Card Layout Guidelines
Adapter Card Routing Recommendations Sheet 1 of
Table 15. Adapter Card Routing Recommendations Sheet 2 of
PCI Express Layout
Intel 41210 Serial to Parallel PCI Bridge Design Guide
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PCI Express Layout
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Circuit Implementations
10.1 41210 Bridge Analog Voltage Filters
Circuit Implementations
10.1.1 PCI Analog Voltage Filters
10.1.2 PCI Express Analog Voltage Filter
Figure 23. PCI Analog Voltage Filter Circuit
10.1.3 Bandgap Analog Voltage Filter
Figure 24. PCI Express Analog Voltage Filter Circuit
Circuit Implementations
Bandgap Analog Voltage Filter Circuit
Circuit Implementations
B2726
Figure 26. Reference and Compensation Circuit Implementations
Circuit Implementations
Table 17. SMBUs Address Configuration
10.2.1 SM Bus
Circuit Implementations
11.1 Board Stack-up
41210 Bridge Customer Reference
Boards
Intel 41210 Serial to Parallel PCI Bridge Design Guide
41210 Bridge Customer Reference Boards
11.2 Material
11.3 Impedance
Table 18. CRB Board Stackup
41210 Bridge Customer Reference Boards
11.4 Board Outline
Figure 27. Mechanical Outline of the 41210 Bridge
U1 Intelfi Bridge
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41210 Bridge Customer Reference Boards
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Design Guide Checklist
Table 19. PCI Express Interface Signals
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Design Guide Checklist
Table 20. PCI/PCI-X Interface Signals
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Design Guide Checklist
Table 20. PCI/PCI-X Interface Signals
Design without secondary PCI/PCI
Design Guide Checklist
Table 21. Miscellaneous Signals
Table 22. SMBus Interface Signals
To retry configuration accesses to the 41210, pull high to
power down or any other time during system operation
Table 23. Power and Ground Signals
Design Guide Checklist
Intel 41210 Serial to Parallel PCI Bridge Design Guide
Table 24. JTAG Signals
Design Guide Checklist
Intel 41210 Serial to Parallel PCI Bridge Design Guide
