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Intel 41210 Embedded PCI-X 100 MHz Topology, Embedded PCI-X 100 MHz Routing Recommendations

Models: 41210

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8.6.2Embedded PCI-X 100 MHz

PCI-X Layout Guidelines

8.6.2Embedded PCI-X 100 MHz

This section lists the embedded routing recommendations for PCI-X 100 MHz. Figure 19 shows the block diagram of this topology and Table 11 describes the routing recommendations.

Figure 19. Embedded PCI-X 100 MHz Topology

TL_EM1 EM1

TL1

TL_EM3 EM3

TL_EM2 EM2

B2720 -01

Table 11.	Embedded PCI-X 100 MHz Routing Recommendations

	Parameter	Routing Guideline for Lower AD Bus

	Reference Plane	Route over an unbroken ground plane

	Board Impedance	60 Ω +/- 15%

	Stripline Trace Spacing	12 mils from edge to edge

	Microstrip Trace Spacing	18 mils, from edge to edge

	Break Out	5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils

	Group Spacing	Spacing from other groups: 25 mils min, edge to edge

	Trace Length 1 (TL1): From
	41210 Bridge signal Ball to	0.5” min - 3.0” max
	first junction

	Trace Length: TL_EM1: from
	41210 Bridge signal ball to	2.5” min - 3.5” max
	the first embedded device
	Trace Length TL_EM2 -
	TL_EM3: from junction to the	1.5” min - 3.5” max
	embedded device

	Length Matching	Clocks coming form the clock driver must be on the same layer and length
	Requirements:	matched to within 25 mils.

	Number of vias	4 vias max per path

40	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

Image 40

Intel 41210 Embedded PCI-X 100 MHz Topology, Embedded PCI-X 100 MHz Routing Recommendations, PCI-X Layout Guidelines

Contents

Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents ContentsIntroduction Figures ContentsTables Revision HistoryContents SMBUs Address ConfigurationContents This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 1.1 Terminology and Definitions About This DocumentTable 1. Terminology and Definitions Sheet 1 of Table 1. Terminology and Definitions Sheet 2 of About This DocumentIntel 41210 Serial to Parallel PCI Bridge Design Guide 2.2 PCI-X Interface Features 2.1 PCI Express Interface FeaturesIntroduction2 2.3 Power Management 2.4.1 SMBus for configuration register initialization2.4 SMBus Interface IntroductionFigure 1. 41210 Bridge Microcontroller Block Diagram 2.4.2 Microcontroller Connections to the 41210 BridgeFigure 2. 41210 Bridge Microcontroller Connections ConfigurationFigure 3. 41210 Bridge Block Diagram 2.5 JTAG2.6 Related Documents Intelﬁ 41210 Bridge A2.7 Intel41210 Serial to Parallel PCI Bridge Applications Figure 4. Intel 41210 Bridge Adapter Card Block DiagramIntroduction Introduction This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 3.1 Package Specification Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package DimensionsPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Package InformationB2711-01 Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide B2712-01Package Information This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide Power Plane Layout 4.1 41210 Bridge Decoupling GuidelinesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuideCapacitor Legend B2714-014.2 Split Voltage Planes Table 2. 41210 Bridge Decoupling GuidelinesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuideFigure 10. 41210 Bridge Single-Layer Split Voltage Plane Power Plane LayoutPCI Express Core5.1 ARST#,BRST# and PERST# Timing Requirements 41210 Bridge Reset and Power Timing Considerations55.2 VCC15 and VCC33 Voltage Requirements This page intentionally left blank 41210 Bridge Reset and Power Timing ConsiderationsIntel 41210 Serial to Parallel PCI Bridge Design Guide 6.1 General Routing Guidelines General Routing Guidelines6.2 Crosstalk Figure 12. PCB Ground Layout Around Connectors 6.3 EMI ConsiderationsGeneral Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height6.4 Power Distribution and Decoupling 6.5 Trace Impedance6.4.1 Decoupling http//emclab.umr.edu/pcbtlc6.5.1 Differential Impedance Figure 13. Cross Section of Differential TraceFigure 14. Two-by-two Differential Impedance Matrix Z11 Z12 Z21 Z227.1 Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Figure 15. Adapter Card Stackup Board Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide 8.1 Interrupts PCI-X Layout GuidelinesTable 4. INTx Routing Table 8.2 PCI Arbitration 8.1.1 Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Table 5. Interrupt Binding for Devices Behind a Bridge8.3 PCI General Layout Guidelines 8.2.1 PCI Resistor CompensationFigure 16. PCI RCOMP PCI-X Layout GuidelinesTable 6. PCI-X Signals 8.3.1 PCI Pullup Resistors Not RequiredTable 7. PCI/PCI-X Frequency/Mode Straps PCI-X Layout Guidelines8.4 PCI Clock Layout Guidelines PCI-X Layout GuidelinesFigure 17. PCI Clock Distribution and Matching Requirements PCI-X Layout GuidelinesIntel 41210 Bridge PCI Device PCI Device PCI Device PCI Device PCI DevicePCI-X Clock Layout Requirements Summary PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide ParameterPCI-X Slot Guidelines 8.5 PCI-X Topology Layout GuidelinesPCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHz Figure 18. Embedded PCI-X 133 MHz TopologyEmbedded PCI-X 133 MHz Routing Recommendations PCI-X Layout Guidelines8.6.2 Embedded PCI-X 100 MHz Figure 19. Embedded PCI-X 100 MHz TopologyEmbedded PCI-X 100 MHz Routing Recommendations PCI-X Layout Guidelines8.6.3 PCI-X 66 MHz Embedded Topology Figure 20. PCI-X 66 MHz Embedded Routing TopologyPCI-X 66 MHz Embedded Routing Recommendations PCI-X Layout Guidelines8.6.4 PCI 66 MHz Embedded Topology Figure 21. PCI 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI-X Layout Guidelines8.6.5 PCI 33 MHz Embedded Mode Topology Figure 22. PCI 33 MHz Embedded Mode Routing TopologyPCI 33 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesPCI-X Layout Guidelines This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI Express Layout 9.1 General recommendations9.2 PCI-Express Layout Guidelines 9.3 Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 ofPCI Express Layout Table 15. Adapter Card Routing Recommendations Sheet 2 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI Express Layout This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide Circuit Implementations 10.1 41210 Bridge Analog Voltage Filters10.1.1 PCI Analog Voltage Filters 10.1.2 PCI Express Analog Voltage FilterCircuit Implementations Figure 23. PCI Analog Voltage Filter CircuitFigure 24. PCI Express Analog Voltage Filter Circuit 10.1.3 Bandgap Analog Voltage FilterCircuit Implementations Circuit Implementations Bandgap Analog Voltage Filter CircuitB2726 Figure 26. Reference and Compensation Circuit Implementations Circuit Implementations10.2.1 SM Bus Table 17. SMBUs Address ConfigurationCircuit Implementations 41210 Bridge Customer Reference Boards11.1 Board Stack-up Intel 41210 Serial to Parallel PCI Bridge Design Guide11.2 Material 11.3 Impedance41210 Bridge Customer Reference Boards Table 18. CRB Board Stackup11.4 Board Outline Figure 27. Mechanical Outline of the 41210 Bridge41210 Bridge Customer Reference Boards U1 Intelﬁ Bridge41210 Bridge Customer Reference Boards This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 19. PCI Express Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 20. PCI/PCI-X Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 20. PCI/PCI-X Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCITable 21. Miscellaneous Signals Table 22. SMBus Interface SignalsDesign Guide Checklist To retry configuration accesses to the 41210, pull high toTable 23. Power and Ground Signals Design Guide Checklistpower down or any other time during system operation Intel 41210 Serial to Parallel PCI Bridge Design GuideDesign Guide Checklist Table 24. JTAG SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide