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Intel 41210 manual Bridge Reset and Power Timing Considerations5

Models: 41210

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41210 Bridge Reset and Power Timing

41210 Bridge Reset and Power Timing

Considerations5

This chapter describes the 41210 Bridge reset timing considerations.

5.1A_RST#,B_RST# and PERST# Timing Requirements

The PCI-X Specification requires that there is a 100ms delay from valid power (PERST#) to reset deassertion (A_RST#/B_RST#). 41210 Bridge will keep A_RST#/B_RST# asserted for a minimum of 320ms after PERST# is deasserted.

5.2VCC15 and VCC33 Voltage Requirements

The following steps are the power sequencing requirements that must be followed with the

41210 Bridge:

1.The 41210 Bridge requires that the VCC33 voltage rail be no less than 0.5V below VCC15 (absolute voltage value) at all times during 41210 operation, including during system power up and power down. In other words, the following must always be true:

VCC33 >= (VCC15 – 0.5V)

This can be accomplished by placing a diode (with a voltage drop <0.5V) between VCC15 and VCC33. A node will be connected to VCC15 and cathode will be connected to VCC33.

If VCC15 (1.5V PCI-X I/O voltage) and VCC15 (1.5V core voltage) are tied together on the platform, then both voltages must meet the above rule.

Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies.

2.If a voltage regulator solution is used which shunts VCC15 to ground while VCC33 is powered, the maximum allowable time that VCC15 can be shunted to ground while VCC33 is fully powered is 20ms.

3.The maximum allowed time between VCC33 and VCC15 ramping is 525ms.

Note: There is no minimum sequencing time requirement other than requirements in Steps 2 and 3.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 manual Bridge Reset and Power Timing Considerations5, ARST#,BRST# and PERST# Timing Requirements

Contents

Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Introduction ContentsContents Contents FiguresSMBUs Address Configuration TablesRevision History ContentsIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankContents Table 1. Terminology and Definitions Sheet 1 of About This Document1.1 Terminology and Definitions Intel 41210 Serial to Parallel PCI Bridge Design Guide About This DocumentTable 1. Terminology and Definitions Sheet 2 of Introduction2 2.1 PCI Express Interface Features2.2 PCI-X Interface Features Introduction 2.3 Power Management2.4.1 SMBus for configuration register initialization 2.4 SMBus InterfaceConfiguration Figure 1. 41210 Bridge Microcontroller Block Diagram2.4.2 Microcontroller Connections to the 41210 Bridge Figure 2. 41210 Bridge Microcontroller ConnectionsIntelﬁ 41210 Bridge A Figure 3. 41210 Bridge Block Diagram2.5 JTAG 2.6 Related DocumentsIntroduction Figure 4. Intel 41210 Bridge Adapter Card Block Diagram2.7 Intel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankIntroduction Intel 41210 Serial to Parallel PCI Bridge Design Guide 3.1 Package SpecificationFigure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions Package InformationB2711-01 Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide B2712-01 Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package DimensionsPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPackage Information 4.1 41210 Bridge Decoupling Guidelines Power Plane LayoutB2714-01 Power Plane LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Capacitor LegendIntel 41210 Serial to Parallel PCI Bridge Design Guide 4.2 Split Voltage PlanesTable 2. 41210 Bridge Decoupling Guidelines Power Plane LayoutCore Figure 10. 41210 Bridge Single-Layer Split Voltage PlanePower Plane Layout PCI Express5.2 VCC15 and VCC33 Voltage Requirements 41210 Bridge Reset and Power Timing Considerations55.1 ARST#,BRST# and PERST# Timing Requirements Intel 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Reset and Power Timing ConsiderationsThis page intentionally left blank 6.2 Crosstalk General Routing Guidelines6.1 General Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height Figure 12. PCB Ground Layout Around Connectors6.3 EMI Considerations General Routing Guidelineshttp//emclab.umr.edu/pcbtlc 6.4 Power Distribution and Decoupling6.5 Trace Impedance 6.4.1 DecouplingZ11 Z12 Z21 Z22 6.5.1 Differential ImpedanceFigure 13. Cross Section of Differential Trace Figure 14. Two-by-two Differential Impedance MatrixAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines7.1 Adapter Card Topology Intel 41210 Serial to Parallel PCI Bridge Design Guide Board Layout GuidelinesFigure 15. Adapter Card Stackup Table 4. INTx Routing Table PCI-X Layout Guidelines8.1 Interrupts Table 5. Interrupt Binding for Devices Behind a Bridge 8.2 PCI Arbitration8.1.1 Interrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI-X Layout Guidelines 8.3 PCI General Layout Guidelines8.2.1 PCI Resistor Compensation Figure 16. PCI RCOMPPCI-X Layout Guidelines Table 6. PCI-X Signals8.3.1 PCI Pullup Resistors Not Required Table 7. PCI/PCI-X Frequency/Mode StrapsPCI-X Layout Guidelines 8.4 PCI Clock Layout GuidelinesPCI Device PCI Device PCI Device PCI Device PCI Device Figure 17. PCI Clock Distribution and Matching RequirementsPCI-X Layout Guidelines Intel 41210 BridgeParameter PCI-X Clock Layout Requirements SummaryPCI-X Layout Guidelines Intel 41210 Serial to Parallel PCI Bridge Design GuidePCI-X Layout Guidelines 8.5 PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines PCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHzFigure 18. Embedded PCI-X 133 MHz Topology Embedded PCI-X 133 MHz Routing RecommendationsPCI-X Layout Guidelines 8.6.2 Embedded PCI-X 100 MHzFigure 19. Embedded PCI-X 100 MHz Topology Embedded PCI-X 100 MHz Routing RecommendationsPCI-X Layout Guidelines 8.6.3 PCI-X 66 MHz Embedded TopologyFigure 20. PCI-X 66 MHz Embedded Routing Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI-X Layout Guidelines 8.6.4 PCI 66 MHz Embedded TopologyFigure 21. PCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI-X Layout Guidelines 8.6.5 PCI 33 MHz Embedded Mode TopologyFigure 22. PCI 33 MHz Embedded Mode Routing Topology PCI 33 MHz Embedded Routing RecommendationsIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPCI-X Layout Guidelines 9.1 General recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 of 9.2 PCI-Express Layout Guidelines9.3 Adapter Card Layout Guidelines PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 15. Adapter Card Routing Recommendations Sheet 2 ofPCI Express Layout Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPCI Express Layout 10.1 41210 Bridge Analog Voltage Filters Circuit ImplementationsFigure 23. PCI Analog Voltage Filter Circuit 10.1.1 PCI Analog Voltage Filters10.1.2 PCI Express Analog Voltage Filter Circuit ImplementationsCircuit Implementations 10.1.3 Bandgap Analog Voltage FilterFigure 24. PCI Express Analog Voltage Filter Circuit B2726 Bandgap Analog Voltage Filter CircuitCircuit Implementations Circuit Implementations Figure 26. Reference and Compensation Circuit ImplementationsCircuit Implementations Table 17. SMBUs Address Configuration10.2.1 SM Bus Intel 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Customer ReferenceBoards 11.1 Board Stack-upTable 18. CRB Board Stackup 11.2 Material11.3 Impedance 41210 Bridge Customer Reference BoardsU1 Intelﬁ Bridge 11.4 Board OutlineFigure 27. Mechanical Outline of the 41210 Bridge 41210 Bridge Customer Reference BoardsIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blank41210 Bridge Customer Reference Boards Intel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide ChecklistTable 19. PCI Express Interface Signals Intel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide ChecklistTable 20. PCI/PCI-X Interface Signals Design without secondary PCI/PCI Design Guide ChecklistTable 20. PCI/PCI-X Interface Signals Intel 41210 Serial to Parallel PCI Bridge Design GuideTo retry configuration accesses to the 41210, pull high to Table 21. Miscellaneous SignalsTable 22. SMBus Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 23. Power and Ground SignalsDesign Guide Checklist power down or any other time during system operationIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 24. JTAG SignalsDesign Guide Checklist