Bridge Reset and Power Timing Considerations5 | Intel 41210 specs

41210 Bridge Reset and Power Timing

Considerations5

This chapter describes the 41210 Bridge reset timing considerations.

5.1A_RST#,B_RST# and PERST# Timing Requirements

The PCI-X Specification requires that there is a 100ms delay from valid power (PERST#) to reset deassertion (A_RST#/B_RST#). 41210 Bridge will keep A_RST#/B_RST# asserted for a minimum of 320ms after PERST# is deasserted.

5.2VCC15 and VCC33 Voltage Requirements

The following steps are the power sequencing requirements that must be followed with the

41210 Bridge:

1.The 41210 Bridge requires that the VCC33 voltage rail be no less than 0.5V below VCC15 (absolute voltage value) at all times during 41210 operation, including during system power up and power down. In other words, the following must always be true:

VCC33 >= (VCC15 – 0.5V)

This can be accomplished by placing a diode (with a voltage drop <0.5V) between VCC15 and VCC33. A node will be connected to VCC15 and cathode will be connected to VCC33.

If VCC15 (1.5V PCI-X I/O voltage) and VCC15 (1.5V core voltage) are tied together on the platform, then both voltages must meet the above rule.

Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies.

2.If a voltage regulator solution is used which shunts VCC15 to ground while VCC33 is powered, the maximum allowable time that VCC15 can be shunted to ground while VCC33 is fully powered is 20ms.

3.The maximum allowed time between VCC33 and VCC15 ramping is 525ms.

Note: There is no minimum sequencing time requirement other than requirements in Steps 2 and 3.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 manual Bridge Reset and Power Timing Considerations5, ARST#,BRST# and PERST# Timing Requirements

Contents

Design Guide Intel 41210 Serial to Parallel PCI Bridge Intel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Description TablesRevision History This page intentionally left blank Term Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1 Terminology and Definitions Sheet 2 About This Document Introduction2 PCI Express Interface FeaturesPCI-X Interface Features Introduction Power ManagementSMBus for configuration register initialization SMBus Interface Microcontroller Connections to the 41210 Bridge Bridge Microcontroller Block Diagram Related Documents Jtag Intel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Bridge Adapter Card Block Diagram This page intentionally left blank Package Information Package Specification Package Information Bottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Side View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank 41210 Bridge Decoupling Guidelines Power Plane Layout Power Plane Layout Bridge Decoupling Guidelines Split Voltage Planes PCI VCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations5ARST#,BRST# and PERST# Timing Requirements Bridge Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines General Routing Guidelines EMI Considerations Decoupling Power Distribution and DecouplingTrace Impedance Cross Section of Differential Trace Differential Impedance Adapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Adapter Card Stackup Board Layout Guidelines INTx Routing Table PCI-X Layout GuidelinesInterrupts Interrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout Guidelines PCI Resistor Compensation PCI General Layout Guidelines PCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Pullup Resistors Not Required BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Layout Guidelines PCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary PCI-X Slot Guidelines PCI-X Topology Layout Guidelines Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHz PCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 66 MHz Embedded Topology PCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode Topology This page intentionally left blank General recommendations PCI Express Layout Adapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express Layout Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank 10.1 41210 Bridge Analog Voltage Filters ConfigCircuit Implementations Circuit Implementations PCI Analog Voltage FiltersPCI Express Analog Voltage Filter Vssape Bandgap Analog Voltage FilterVccape VSS Vssbgpe Bandgap Analog Voltage Filter CircuitVccbgpe PERCOMP0 PERCOMP1 Rcomp Reference and Compensation Circuit Implementations Bit Value SMBUs Address ConfigurationSM Bus Board Stack-up Bridge Customer Reference Boards Bridge Customer Reference Boards Layer Type Thickness Copper WeightMaterial Impedance Mechanical Outline of the 41210 Bridge Board Outline This page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/Impact PCI/PCI-X Interface Signals Design Guide Checklist Bpcixcap AM66ENBM66EN PERST# Apcixcap Signals Miscellaneous SignalsSMBus Interface Signals VCC33 Power and Ground SignalsSignal Recommendations Reason/Impact VCC15 Jtag Signals